da850evm.c 8.3 KB

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  1. /*
  2. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * Based on da830evm.c. Original Copyrights follow:
  5. *
  6. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  7. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <common.h>
  24. #include <i2c.h>
  25. #include <net.h>
  26. #include <netdev.h>
  27. #include <asm/arch/hardware.h>
  28. #include <asm/arch/emif_defs.h>
  29. #include <asm/arch/emac_defs.h>
  30. #include <asm/io.h>
  31. #include <asm/arch/davinci_misc.h>
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
  34. /* SPI0 pin muxer settings */
  35. static const struct pinmux_config spi1_pins[] = {
  36. { pinmux(5), 1, 1 },
  37. { pinmux(5), 1, 2 },
  38. { pinmux(5), 1, 4 },
  39. { pinmux(5), 1, 5 }
  40. };
  41. /* UART pin muxer settings */
  42. static const struct pinmux_config uart_pins[] = {
  43. { pinmux(0), 4, 6 },
  44. { pinmux(0), 4, 7 },
  45. { pinmux(4), 2, 4 },
  46. { pinmux(4), 2, 5 }
  47. };
  48. #ifdef CONFIG_DRIVER_TI_EMAC
  49. static const struct pinmux_config emac_pins[] = {
  50. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  51. { pinmux(14), 8, 2 },
  52. { pinmux(14), 8, 3 },
  53. { pinmux(14), 8, 4 },
  54. { pinmux(14), 8, 5 },
  55. { pinmux(14), 8, 6 },
  56. { pinmux(14), 8, 7 },
  57. { pinmux(15), 8, 1 },
  58. #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */
  59. { pinmux(2), 8, 1 },
  60. { pinmux(2), 8, 2 },
  61. { pinmux(2), 8, 3 },
  62. { pinmux(2), 8, 4 },
  63. { pinmux(2), 8, 5 },
  64. { pinmux(2), 8, 6 },
  65. { pinmux(2), 8, 7 },
  66. { pinmux(3), 8, 0 },
  67. { pinmux(3), 8, 1 },
  68. { pinmux(3), 8, 2 },
  69. { pinmux(3), 8, 3 },
  70. { pinmux(3), 8, 4 },
  71. { pinmux(3), 8, 5 },
  72. { pinmux(3), 8, 6 },
  73. { pinmux(3), 8, 7 },
  74. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  75. { pinmux(4), 8, 0 },
  76. { pinmux(4), 8, 1 }
  77. };
  78. /* I2C pin muxer settings */
  79. static const struct pinmux_config i2c_pins[] = {
  80. { pinmux(4), 2, 2 },
  81. { pinmux(4), 2, 3 }
  82. };
  83. #ifdef CONFIG_NAND_DAVINCI
  84. const struct pinmux_config nand_pins[] = {
  85. { pinmux(7), 1, 1 },
  86. { pinmux(7), 1, 2 },
  87. { pinmux(7), 1, 4 },
  88. { pinmux(7), 1, 5 },
  89. { pinmux(9), 1, 0 },
  90. { pinmux(9), 1, 1 },
  91. { pinmux(9), 1, 2 },
  92. { pinmux(9), 1, 3 },
  93. { pinmux(9), 1, 4 },
  94. { pinmux(9), 1, 5 },
  95. { pinmux(9), 1, 6 },
  96. { pinmux(9), 1, 7 },
  97. { pinmux(12), 1, 5 },
  98. { pinmux(12), 1, 6 }
  99. };
  100. #endif
  101. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  102. #define HAS_RMII 1
  103. #else
  104. #define HAS_RMII 0
  105. #endif
  106. #endif /* CONFIG_DRIVER_TI_EMAC */
  107. static const struct pinmux_resource pinmuxes[] = {
  108. #ifdef CONFIG_SPI_FLASH
  109. PINMUX_ITEM(spi1_pins),
  110. #endif
  111. PINMUX_ITEM(uart_pins),
  112. PINMUX_ITEM(i2c_pins),
  113. #ifdef CONFIG_NAND_DAVINCI
  114. PINMUX_ITEM(nand_pins),
  115. #endif
  116. };
  117. static const struct lpsc_resource lpsc[] = {
  118. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  119. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  120. { DAVINCI_LPSC_EMAC }, /* image download */
  121. { DAVINCI_LPSC_UART2 }, /* console */
  122. { DAVINCI_LPSC_GPIO },
  123. };
  124. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  125. #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
  126. #endif
  127. /*
  128. * get_board_rev() - setup to pass kernel board revision information
  129. * Returns:
  130. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  131. * 0000b - 300 MHz
  132. * 0001b - 372 MHz
  133. * 0010b - 408 MHz
  134. * 0011b - 456 MHz
  135. */
  136. u32 get_board_rev(void)
  137. {
  138. char *s;
  139. u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
  140. u32 rev = 0;
  141. s = getenv("maxcpuclk");
  142. if (s)
  143. maxcpuclk = simple_strtoul(s, NULL, 10);
  144. if (maxcpuclk >= 456000000)
  145. rev = 3;
  146. else if (maxcpuclk >= 408000000)
  147. rev = 2;
  148. else if (maxcpuclk >= 372000000)
  149. rev = 1;
  150. return rev;
  151. }
  152. int board_init(void)
  153. {
  154. #ifndef CONFIG_USE_IRQ
  155. irq_init();
  156. #endif
  157. #ifdef CONFIG_NAND_DAVINCI
  158. /*
  159. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  160. * Linux kernel @ 25MHz EMIFA
  161. */
  162. writel((DAVINCI_ABCR_WSETUP(0) |
  163. DAVINCI_ABCR_WSTROBE(0) |
  164. DAVINCI_ABCR_WHOLD(0) |
  165. DAVINCI_ABCR_RSETUP(0) |
  166. DAVINCI_ABCR_RSTROBE(1) |
  167. DAVINCI_ABCR_RHOLD(0) |
  168. DAVINCI_ABCR_TA(0) |
  169. DAVINCI_ABCR_ASIZE_8BIT),
  170. &davinci_emif_regs->ab2cr); /* CS3 */
  171. #endif
  172. /* arch number of the board */
  173. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
  174. /* address of boot parameters */
  175. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  176. /*
  177. * Power on required peripherals
  178. * ARM does not have access by default to PSC0 and PSC1
  179. * assuming here that the DSP bootloader has set the IOPU
  180. * such that PSC access is available to ARM
  181. */
  182. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  183. return 1;
  184. /* setup the SUSPSRC for ARM to control emulation suspend */
  185. writel(readl(&davinci_syscfg_regs->suspsrc) &
  186. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  187. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  188. DAVINCI_SYSCFG_SUSPSRC_UART2),
  189. &davinci_syscfg_regs->suspsrc);
  190. /* configure pinmux settings */
  191. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  192. return 1;
  193. #ifdef CONFIG_DRIVER_TI_EMAC
  194. if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
  195. return 1;
  196. davinci_emac_mii_mode_sel(HAS_RMII);
  197. #endif /* CONFIG_DRIVER_TI_EMAC */
  198. /* enable the console UART */
  199. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  200. DAVINCI_UART_PWREMU_MGMT_UTRST),
  201. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  202. return 0;
  203. }
  204. #ifdef CONFIG_DRIVER_TI_EMAC
  205. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  206. /**
  207. * rmii_hw_init
  208. *
  209. * DA850/OMAP-L138 EVM can interface to a daughter card for
  210. * additional features. This card has an I2C GPIO Expander TCA6416
  211. * to select the required functions like camera, RMII Ethernet,
  212. * character LCD, video.
  213. *
  214. * Initialization of the expander involves configuring the
  215. * polarity and direction of the ports. P07-P05 are used here.
  216. * These ports are connected to a Mux chip which enables only one
  217. * functionality at a time.
  218. *
  219. * For RMII phy to respond, the MII MDIO clock has to be disabled
  220. * since both the PHY devices have address as zero. The MII MDIO
  221. * clock is controlled via GPIO2[6].
  222. *
  223. * This code is valid for Beta version of the hardware
  224. */
  225. int rmii_hw_init(void)
  226. {
  227. const struct pinmux_config gpio_pins[] = {
  228. { pinmux(6), 8, 1 }
  229. };
  230. u_int8_t buf[2];
  231. unsigned int temp;
  232. int ret;
  233. /* PinMux for GPIO */
  234. if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
  235. return 1;
  236. /* I2C Exapnder configuration */
  237. /* Set polarity to non-inverted */
  238. buf[0] = 0x0;
  239. buf[1] = 0x0;
  240. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
  241. if (ret) {
  242. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  243. CONFIG_SYS_I2C_EXPANDER_ADDR);
  244. return ret;
  245. }
  246. /* Configure P07-P05 as outputs */
  247. buf[0] = 0x1f;
  248. buf[1] = 0xff;
  249. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
  250. if (ret) {
  251. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  252. CONFIG_SYS_I2C_EXPANDER_ADDR);
  253. }
  254. /* For Ethernet RMII selection
  255. * P07(SelA)=0
  256. * P06(SelB)=1
  257. * P05(SelC)=1
  258. */
  259. if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  260. printf("\nExpander @ 0x%02x read FAILED!!!\n",
  261. CONFIG_SYS_I2C_EXPANDER_ADDR);
  262. }
  263. buf[0] &= 0x1f;
  264. buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
  265. if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  266. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  267. CONFIG_SYS_I2C_EXPANDER_ADDR);
  268. }
  269. /* Set the output as high */
  270. temp = REG(GPIO_BANK2_REG_SET_ADDR);
  271. temp |= (0x01 << 6);
  272. REG(GPIO_BANK2_REG_SET_ADDR) = temp;
  273. /* Set the GPIO direction as output */
  274. temp = REG(GPIO_BANK2_REG_DIR_ADDR);
  275. temp &= ~(0x01 << 6);
  276. REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
  277. return 0;
  278. }
  279. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  280. /*
  281. * Initializes on-board ethernet controllers.
  282. */
  283. int board_eth_init(bd_t *bis)
  284. {
  285. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  286. /* Select RMII fucntion through the expander */
  287. if (rmii_hw_init())
  288. printf("RMII hardware init failed!!!\n");
  289. #endif
  290. if (!davinci_emac_initialize()) {
  291. printf("Error: Ethernet init failed!\n");
  292. return -1;
  293. }
  294. return 0;
  295. }
  296. #endif /* CONFIG_DRIVER_TI_EMAC */