u-boot: iomux-vf610: Adding the quadspi iomux settings

Add the iomux settings for quadspi in the enumeration list. This
will set the SCK, CSO and IO pads for both quadspi0 and quadspi1

Signed-off-by: Juan Gutierrez <b44802@freescale.com>

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -32,7 +32,12 @@
 #define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
 
 #define VF610_USB_PAD_CTRL	(PAD_CTL_PUS_100K_UP | \
-			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+				PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+
+
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
@@ -98,8 +103,26 @@ enum {
 	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_PTD6__GPIO85              = IOMUX_PAD(0x0154, 0x0154, 0, __NA_, 0, VF610_USB_PAD_CTRL),
-	VF610_PAD_PTD13__GPIO92             = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_PTD6__GPIO85			= IOMUX_PAD(0x0154, 0x0154, 0, __NA_, 0, VF610_USB_PAD_CTRL),
+	VF610_PAD_PTD13__GPIO92			= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_PTD0__QSCKA			= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__QCS0A			= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__QIO3A			= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD3__QIO2A			= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD4__QIO1A			= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD5__QIO0A			= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD7__QSCKB			= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD8__QCS0B			= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__QIO3B			= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD10__QIO2B			= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD11__QIO1B			= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD12__QIO0B			= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTA19__QSCKA			= IOMUX_PAD(0x0024, 0x0024, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTB0__QCS0A			= IOMUX_PAD(0x0058, 0x0058, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTB1__QIO3A			= IOMUX_PAD(0x005C, 0x005C, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTB2__QIO2A			= IOMUX_PAD(0x0060, 0x0060, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTB3__QIO1A			= IOMUX_PAD(0x0064, 0x0064, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTB4__QIO0A			= IOMUX_PAD(0x0068, 0x0068, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
 };
 
 #endif	/* __IOMUX_VF610_H__ */