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@@ -720,7 +720,7 @@ int mxs_get_vddio_power_source_off(void)
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tmp = readl(&power_regs->hw_power_vddioctrl);
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if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
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if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
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- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
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+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
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return 1;
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}
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}
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@@ -728,7 +728,7 @@ int mxs_get_vddio_power_source_off(void)
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if (!(readl(&power_regs->hw_power_5vctrl) &
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POWER_5VCTRL_ENABLE_DCDC)) {
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if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
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- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
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+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
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return 1;
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}
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}
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@@ -776,7 +776,7 @@ void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
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uint32_t cur_target, diff, bo_int = 0;
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uint32_t powered_by_linreg = 0;
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- new_brownout = new_target - new_brownout;
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+ new_brownout = (new_target - new_brownout + 25) / 50;
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cur_target = readl(&power_regs->hw_power_vddioctrl);
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cur_target &= POWER_VDDIOCTRL_TRG_MASK;
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@@ -862,8 +862,8 @@ void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
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}
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clrsetbits_le32(&power_regs->hw_power_vddioctrl,
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- POWER_VDDDCTRL_BO_OFFSET_MASK,
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- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
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+ POWER_VDDIOCTRL_BO_OFFSET_MASK,
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+ new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
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}
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void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
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@@ -873,7 +873,7 @@ void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
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uint32_t cur_target, diff, bo_int = 0;
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uint32_t powered_by_linreg = 0;
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- new_brownout = new_target - new_brownout;
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+ new_brownout = (new_target - new_brownout + 12) / 25;
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cur_target = readl(&power_regs->hw_power_vdddctrl);
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cur_target &= POWER_VDDDCTRL_TRG_MASK;
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