Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
@@ -140,7 +140,7 @@ phys_size_t initdram (int board_type)
uint *p = 0;
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
+
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
*p = (unsigned int)0xdeadbeef;
@@ -341,7 +341,7 @@ phys_size_t initdram (int board_type)
@@ -261,7 +261,9 @@ void cpu_init_f (void)
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
-
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
}
@@ -77,8 +77,6 @@ ddr_enable_ecc(unsigned int dram_size)
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
@@ -113,6 +113,9 @@ void cpu_init_f(void)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);