Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

board/atum8548/atum8548.c

@@ -37,10 +37,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int board_early_init_f (void)
@@ -117,12 +113,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/mpc8536ds/mpc8536ds.c

@@ -41,10 +41,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 phys_size_t fixed_sdram(void);
 
 int checkboard (void)
@@ -65,20 +61,12 @@ initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/mpc8544ds/mpc8544ds.c

@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -77,12 +73,6 @@ initdram(int board_type)
 
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/mpc8548cds/mpc8548cds.c

@@ -38,10 +38,6 @@
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -56,7 +52,6 @@ int checkboard (void)
 	uint pci_slot = get_pci_slot ();
 
 	uint cpu_board_rev = get_cpu_board_revision ();
-	uint svr;
 
 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 		get_board_version (), pci_slot);
@@ -69,17 +64,6 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
-	svr = get_svr();
-
-	/*
-	 * Fix CPU2 errata: A core hang possible while executing a
-	 * msync instruction and a snoopable transaction from an I/O
-	 * master tagged to make quick forward progress is present.
-	 * Fixed in Silicon Rev.2.1
-	 */
-	if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
-		ecm->eebpcr |= (1 << 16);
-
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.
 	 */
@@ -118,13 +102,6 @@ initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
-
 	/*
 	 * SDRAM Initialization
 	 */
@@ -355,7 +332,7 @@ pci_init_board(void)
 		first_free_busno=hose->last_busno+1;
 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			/* PCI-X init */
 			if (CONFIG_SYS_CLK_FREQ < 66000000)
 				printf("PCI-X will only work at 66 MHz\n");

board/freescale/mpc8568mds/mpc8568mds.c

@@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 };
 
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 void local_bus_init(void);
 void sdram_init(void);
 
@@ -170,13 +165,6 @@ initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
-
 	/*
 	 * SDRAM Initialization
 	 */

board/freescale/mpc8572ds/mpc8572ds.c

@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int checkboard (void)
@@ -61,20 +57,12 @@ phys_size_t initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/sbc8548/sbc8548.c

@@ -36,10 +36,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -65,13 +61,6 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
-	/*
-	 * Fix CPU2 errata: A core hang possible while executing a
-	 * msync instruction and a snoopable transaction from an I/O
-	 * master tagged to make quick forward progress is present.
-	 */
-	ecm->eebpcr |= (1 << 16);
-
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.
 	 */
@@ -114,12 +103,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	/*
 	 * SDRAM Initialization
 	 */
@@ -429,7 +412,7 @@ pci_init_board(void)
 		first_free_busno=hose->last_busno+1;
 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			/* PCI-X init */
 			if (CONFIG_SYS_CLK_FREQ < 66000000)
 				printf("PCI-X will only work at 66 MHz\n");

board/socrates/tlb.c

@@ -100,6 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
+#if !defined(CONFIG_SPD_EEPROM)
 	/*
 	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
 	 * 0x00000000  512M	DDR System memory
@@ -114,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/tqc/tqm85xx/tqm85xx.c

@@ -610,7 +610,7 @@ static inline void init_pci1(void)
 
 		first_free_busno = hose->last_busno + 1;
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			ushort reg16 =
 				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
 				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;

cpu/mpc85xx/cpu_init.c

@@ -132,6 +132,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset ((void *) gd, 0, sizeof (gd_t));
+
 	set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		1, 0, BOOKE_PAGESZ_4K, 0);
@@ -140,24 +146,19 @@ void cpu_init_early_f(void)
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 	{
 		u32 temp;
+		volatile u32 *ccsr_virt =
+			(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
 
-		set_tlb(0, CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_DEFAULT,
+		set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			1, 1, BOOKE_PAGESZ_4K, 0);
 
-		temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT);
-		out_be32((volatile u32 *)CONFIG_SYS_CCSRBAR_DEFAULT, CONFIG_SYS_CCSRBAR_PHYS >> 12);
-
+		temp = in_be32(ccsr_virt);
+		out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
 		temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
 	}
 #endif
 
-	/* Pointer is writable since we allocated a register for it */
-	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset ((void *) gd, 0, sizeof (gd_t));
-
 	init_laws();
 	invalidate_tlb(0);
 	init_tlbs();
@@ -174,6 +175,19 @@ void cpu_init_f (void)
 {
 	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	extern void m8560_cpm_reset (void);
+#ifdef CONFIG_MPC8548
+	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	uint svr = get_svr();
+
+	/*
+	 * CPU2 errata workaround: A core hang possible while executing
+	 * a msync instruction and a snoopable transaction from an I/O
+	 * master tagged to make quick forward progress is present.
+	 * Fixed in silicon rev 2.1.
+	 */
+	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
+		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
+#endif
 
 	disable_tlb(14);
 	disable_tlb(15);

cpu/mpc85xx/pci.c

@@ -70,7 +70,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
 	 */
 	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 
-	if (!(gur->pordevsr & PORDEVSR_PCI)) {
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 		/* PCI-X init */
 		if (CONFIG_SYS_CLK_FREQ < 66000000)
 			printf("PCI-X will only work at 66 MHz\n");

cpu/mpc8xxx/ddr/main.c

@@ -475,9 +475,14 @@ phys_size_t fsl_ddr_sdram(void)
 			 */
 			memctl_interleaved = 1;
 		} else {
-			printf("Error: memctl interleaving not "
+			printf("Warning: memctl interleaving not "
 				"properly configured on all controllers\n");
-			while (1);
+			memctl_interleaved = 0;
+			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+				info.memctl_opts[i].memctl_interleaving = 0;
+			debug("Recomputing with memctl_interleaving off.\n");
+			total_memory = fsl_ddr_compute(&info,
+						       STEP_ASSIGN_ADDRESSES);
 		}
 	}
 

cpu/mpc8xxx/ddr/options.c

@@ -197,10 +197,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 */
 	if ((p = getenv("memctl_intlv_ctl")) != NULL) {
 		if (pdimm[0].n_ranks == 0) {
-			printf("There is no rank on CS0. Because only rank on \
-				CS0 and ranks chip-select interleaved with CS0\
-				are controller interleaved, force non memory \
-				controller interleaving\n");
+			printf("There is no rank on CS0. Because only rank on "
+				"CS0 and ranks chip-select interleaved with CS0"
+				" are controller interleaved, force non memory "
+				"controller interleaving\n");
 			popts->memctl_interleaving = 0;
 		} else {
 			popts->memctl_interleaving = 1;
@@ -239,22 +239,22 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 		case FSL_DDR_CS0_CS1:
 			if (pdimm[0].n_ranks != 2) {
 				popts->ba_intlv_ctl = 0;
-				printf("No enough bank(chip-select) for \
-					CS0+CS1, force non-interleaving!\n");
+				printf("Not enough bank(chip-select) for "
+					"CS0+CS1, force non-interleaving!\n");
 			}
 			break;
 		case FSL_DDR_CS2_CS3:
 			if (pdimm[1].n_ranks !=2){
 				popts->ba_intlv_ctl = 0;
-				printf("No enough bank(CS) for CS2+CS3, \
-					force non-interleaving!\n");
+				printf("Not enough bank(CS) for CS2+CS3, "
+					"force non-interleaving!\n");
 			}
 			break;
 		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 			if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
 				popts->ba_intlv_ctl = 0;
-				printf("No enough bank(CS) for CS0+CS1 or \
-					 CS2+CS3, force non-interleaving!\n");
+				printf("Not enough bank(CS) for CS0+CS1 or "
+					"CS2+CS3, force non-interleaving!\n");
 			}
 			break;
 		default:

drivers/pci/fsl_pci_init.c

@@ -58,7 +58,7 @@ void pciauto_config_init(struct pci_controller *hose);
 int fsl_pci_setup_inbound_windows(struct pci_region *r)
 {
 	struct pci_region *rgn_base = r;
-	u64 sz = min((u64)gd->ram_size, 1ull << 32);
+	u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1);
 
 	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
 	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;

include/asm-ppc/fsl_lbc.h

@@ -69,6 +69,14 @@
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
 #endif
 
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
+					 ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
 /* OR - Option Registers
  */
 #define OR0				0x5004		/* Register offset to immr */

include/asm-ppc/immap_85xx.h

@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
+#define MPC85xx_PORDEVSR_PCI1		0x00800000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
@@ -1647,8 +1648,6 @@ typedef struct ccsr_gur {
 	char	res15[61648];	/* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;
 
-#define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
-
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET	(0xE0000)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET	(0x0000)

include/configs/MPC8536DS.h

@@ -99,7 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000

include/configs/MPC8544DS.h

@@ -97,7 +97,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #define CONFIG_DDR_SPD
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000

include/configs/MPC8548CDS.h

@@ -100,7 +100,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/

include/configs/MPC8568MDS.h

@@ -92,7 +92,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 

include/configs/MPC8572DS.h

@@ -99,6 +99,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_DDR_SPD
 #undef CONFIG_DDR_DLL
 
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
@@ -114,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
 
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000

include/configs/MPC8641HPCN.h

@@ -186,17 +186,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS	(CONFIG_SYS_FLASH_BASE \
 					 | CONFIG_SYS_PHYS_ADDR_HIGH)
 
-
 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 
-/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
-#define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
-					 ((x & 0x300000000ULL) >> 19)))
-#else
-#define BR_PHYS_ADDR(x) (x & 0xffff8000)
-#endif
-
 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 				 | 0x00001001)	/* port size 16bit */
 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/