u-boot: vf610_qspi: Initial quadspi driver implementation

This drivers implements the support for:
 - Initialize
 - Programming QuadSPI flash devices A and B for both quadspi0
   and quadspi1
 - Chip Erase
 - Sector Erase

Only commands for writing and initialize are initially supported:

 - qspiinit: for initialize and configure qspi0 or qspi1 (dev)
   and set the flash device top addresses

	qspiiint dev=X <fa1=A1> <fa2=A2> <fb1=B1> <fb2=B2>

 - qspiwrite
	qspiwrite destAddr srcAddr length

  Example:
	qspiinit dev=0 fa1=0x21000000 fb1=0x22000000
	qspiwrite 0x3f800000 0x20000000

Signed-off-by: Juan Gutierrez <b44802@freescale.com>

arch/arm/include/asm/arch-vf610/vf610_qspi.h

@@ -0,0 +1,100 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DRIVERS_SPI_VF600QSPI_H__
+#define __DRIVERS_SPI_VF600QSPI_H__
+
+#define __swap_16(x) \
+		({ unsigned short x_ = (unsigned short)x; \
+		(unsigned short)( \
+			((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
+	       })
+#define __swap_32(x) \
+		({ unsigned long x_ = (unsigned long)x; \
+		(unsigned long)( \
+			((x_ & 0x000000FFUL) << 24) | \
+			((x_ & 0x0000FF00UL) <<  8) | \
+			((x_ & 0x00FF0000UL) >>  8) | \
+			((x_ & 0xFF000000UL) >> 24)); \
+		})
+
+
+#define QSPI_ARDB (*(volatile unsigned int *) 0x7C000000)
+
+/* Lookup Table Instructions */
+#define STOP		0
+#define CMD		1
+#define ADDR		2
+#define DUMMY		3
+#define MODE		4
+#define MODE2		5
+#define MODE4		6
+#define READ		7
+#define WRITE		8
+#define JMP_ON_CS	9
+#define ADDR_DDR	10
+#define MODE_DDR	11
+#define MODE2_DDR	12
+#define MODE4_DDR	13
+#define READ_DDR	14
+#define WRITE_DDR	15
+#define DATA_LEARN	16
+
+#define QSPI_FLASH_PGSZ			0x100
+#define QSPI0_FLASH_BASE_ADDR		0x20000000
+#define QSPI1_FLASH_BASE_ADDR		0x50000000
+
+#ifndef QSPI0_TOP_FLASH_A1_ADDR
+#define QSPI0_TOP_FLASH_A1_ADDR		0x21000000
+#endif
+#ifndef QSPI0_TOP_FLASH_B1_ADDR
+#define QSPI0_TOP_FLASH_B1_ADDR		0x22000000
+#endif
+
+#ifndef QSPI1_TOP_FLASH_A1_ADDR
+#define QSPI1_TOP_FLASH_A1_ADDR		0x51000000
+#endif
+#ifndef QSPI1_TOP_FLASH_B1_ADDR
+#define QSPI1_TOP_FLASH_B1_ADDR		0x52000000
+#endif
+
+/* QuadSPI LUT Bit Fields */
+#define QuadSPI_LUT_OPRND0_MASK		0xFFu
+#define QuadSPI_LUT_OPRND0_SHIFT	0
+#define QuadSPI_LUT_OPRND0(x)		((u32)(((u32)(x))<<QuadSPI_LUT_OPRND0_SHIFT))
+#define QuadSPI_LUT_PAD0_MASK		0x300u
+#define QuadSPI_LUT_PAD0_SHIFT		8
+#define QuadSPI_LUT_PAD0(x)             ((u32)(((u32)(x))<<QuadSPI_LUT_PAD0_SHIFT))
+#define QuadSPI_LUT_INSTR0_MASK		0xFC00u
+#define QuadSPI_LUT_INSTR0_SHIFT	10
+#define QuadSPI_LUT_INSTR0(x)		((u32)(((u32)(x))<<QuadSPI_LUT_INSTR0_SHIFT))
+#define QuadSPI_LUT_OPRND1_MASK		0xFF0000u
+#define QuadSPI_LUT_OPRND1_SHIFT	16
+#define QuadSPI_LUT_OPRND1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_OPRND1_SHIFT))
+#define QuadSPI_LUT_PAD1_MASK		0x3000000u
+#define QuadSPI_LUT_PAD1_SHIFT		24
+#define QuadSPI_LUT_PAD1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_PAD1_SHIFT))
+#define QuadSPI_LUT_INSTR1_MASK		0xFC000000u
+#define QuadSPI_LUT_INSTR1_SHIFT	26
+#define QuadSPI_LUT_INSTR1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_INSTR1_SHIFT))
+
+#endif

drivers/spi/vf610_qspi.c

@@ -0,0 +1,479 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/arch-vf610/iomux-vf610.h>
+#include <asm/arch-vf610/crm_regs.h>
+#include <asm/arch/vf610_qspi.h>
+
+void quadspi_init(void);
+void quadspi_erase(void);
+void quadspi_erase_sector(unsigned int addr);
+void quadspi_program(unsigned int src, unsigned int base, unsigned int size);
+
+static void quadspi_setup_iomux(void);
+static void quadspi_setup_clocks(void);
+static void quadspi_config(void);
+static void quadspi_setup_lut(void);
+static void quadspi_wait_while_flash_busy(void);
+static void quadspi_enable_quadbit(void);
+
+static volatile struct quadspi *qspi = (struct quadspi *)QSPI0_BASE_ADDR;
+static int qspidev = 0;
+static int qspibase = QSPI0_FLASH_BASE_ADDR;
+
+static void quadspi_setup_iomux(void)
+{
+	if (qspidev == 0) {
+	        imx_iomux_v3_setup_pad(VF610_PAD_PTD0__QSCKA);
+	        imx_iomux_v3_setup_pad(VF610_PAD_PTD1__QCS0A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD2__QIO3A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD3__QIO2A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD4__QIO1A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD5__QIO0A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD7__QSCKB);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD8__QCS0B);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD9__QIO3B);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD10__QIO2B);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD11__QIO1B);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTD12__QIO0B);
+	} else {
+		imx_iomux_v3_setup_pad(VF610_PAD_PTA19__QSCKA);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTB0__QCS0A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTB1__QIO3A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTB2__QIO2A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTB3__QIO1A);
+		imx_iomux_v3_setup_pad(VF610_PAD_PTB4__QIO0A);
+	}
+}
+
+static void quadspi_setup_clocks(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+
+	debug ("Setup QuadSPI clocks\n");
+
+	if (qspidev == 0) /* Ungate QSPI0 */
+		ccm->ccgr2 |= 0x1 << 8;
+	else /* Ungate QSPI1 */
+		ccm->ccgr8 |= 0x1 << 8;
+
+	/* Select pll1-pfd4 as source for both Qspi0 and Qsp1 */
+	if (qspidev == 0)
+		ccm->cscmr1 |= (0x3 << 22);
+	else
+		ccm->cscmr1 |= (0x3 << 24);
+
+	/* QSPI Enable, QSPI_DIV(1),
+	 * QSPI_X2_DIV(2), QSPI_X4_DIV(4) = 33MHZ
+	 */
+	if (qspidev == 0)
+		ccm->cscdr3 |= 0x1F;
+	else
+		ccm->cscdr3 |= (0x1F << 8);
+}
+
+static void quadspi_config(void)
+{
+	debug ("Config QuadSPI0\n");
+
+	/* Support both SDR and DDR instructions;
+	 * Enable Qspi module
+	 */
+	qspi->mcr &= ~0x4000;
+	qspi->mcr |= 0x0080;
+
+	qspi->buf0ind = 0x0;
+
+	/* top address of FA1 */
+	if (!qspi->sfa1ad)
+		qspi->sfa1ad = (qspidev ? QSPI1_TOP_FLASH_A1_ADDR
+					: QSPI0_TOP_FLASH_A1_ADDR);
+	/* top address of FA2 */
+	if (!qspi->sfa2ad)
+		qspi->sfa2ad = qspi->sfa1ad;
+	/* top address of FB1 */
+	if (!qspi->sfb1ad)
+		qspi->sfb1ad = (qspidev ? QSPI1_TOP_FLASH_B1_ADDR
+					: QSPI0_TOP_FLASH_B1_ADDR);
+	/* top address of FB2 */
+	if (!qspi->sfb2ad)
+		qspi->sfb2ad = qspi->sfb1ad;
+}
+
+static void quadspi_setup_lut (void)
+{
+	debug ("quadspi_setup_lut\n");
+
+	/* Unlock LUT */
+	qspi->lutkey = 0x5af05af0;
+	qspi->lckcr = 0x2;
+
+	/* seqid 0 - quad read  */
+	qspi->lut[0] = 0x0a1804eb; /* quad read, 24 bit addresses  */
+	qspi->lut[1] = 0x0e0412a5; /* mode bits and 4 dummy cycles  */
+	qspi->lut[2] = 0x24011e80; /* read 128 bytes and jump to address */
+
+	/* seqid 1 - write enable  */
+	qspi->lut[4] = 0x406;
+
+	/* seqid 2 - bulk erase  */
+	qspi->lut[8] = 0x460;
+
+	/* seqid 3 - read status  */
+	qspi->lut[12] = 0x1c010405;
+
+	/* seqid 4 - page program  */
+	qspi->lut[16] = 0x08180402; /* 24bit address  */
+	qspi->lut[17] = 0x2004; /* default 4-byte write  */
+
+	/* seqid 5 - write config/status  */
+	qspi->lut[20] = 0x20020401; /*2-byte write  */
+
+	/* seqid 6 - read config  */
+	qspi->lut[24] = 0x1c010435; /*1-byte read  */
+
+	/* seqid 7 - sector erase  */
+	qspi->lut[28] = 0x081804d8;
+
+	/* seqid 8 - quad ddr read  */
+	/* quad ddr read - 24 bit addresses */
+	qspi->lut[32] =	QuadSPI_LUT_INSTR0(CMD)|
+			QuadSPI_LUT_PAD0(0x0)|
+			QuadSPI_LUT_OPRND0(0xED)|
+			QuadSPI_LUT_INSTR1(ADDR_DDR)|
+			QuadSPI_LUT_PAD1(0x2) |
+			QuadSPI_LUT_OPRND1(0x18);
+
+	/*set mode and 6 dummy cycles */
+	qspi->lut[33] = QuadSPI_LUT_INSTR0(MODE_DDR) |
+			QuadSPI_LUT_PAD0(0x2) |
+			QuadSPI_LUT_OPRND0(0xa5) |
+			QuadSPI_LUT_INSTR1(DUMMY) |
+			QuadSPI_LUT_PAD1(0x2) |
+			QuadSPI_LUT_OPRND1(0x6);
+
+	/* read 128 bytes  */
+	qspi->lut[34] = QuadSPI_LUT_INSTR0(READ_DDR) |
+			QuadSPI_LUT_PAD0(0x2) |
+			QuadSPI_LUT_OPRND0(0x80) |
+			QuadSPI_LUT_INSTR1(JMP_ON_CS) |
+			QuadSPI_LUT_PAD1(0x0) |
+			QuadSPI_LUT_OPRND1(0x1);
+
+	/* seqid 9 - ddr read - 24 bit addresses */
+	qspi->lut[36] = QuadSPI_LUT_INSTR0(CMD) |
+			QuadSPI_LUT_PAD0(0x0) |
+			QuadSPI_LUT_OPRND0(0x0D) |
+			QuadSPI_LUT_INSTR1(ADDR_DDR) |
+			QuadSPI_LUT_PAD1(0x0) |
+			QuadSPI_LUT_OPRND1(0x18);
+
+	/*mode bits and 2 dummy cycles   */
+	qspi->lut[37] = QuadSPI_LUT_INSTR0(MODE_DDR) |
+			QuadSPI_LUT_PAD0(0x0) |
+			QuadSPI_LUT_OPRND0(0xFF) |
+			QuadSPI_LUT_INSTR1(DUMMY)|
+			QuadSPI_LUT_PAD1(0x0) |
+			QuadSPI_LUT_OPRND1(0x2);
+
+	qspi->lut[38] = 0x3880;
+
+	/* lock lut */
+	qspi->lutkey = 0x5af05af0;
+	qspi->lckcr = 0x1;
+
+}
+
+static void quadspi_wait_while_flash_busy(void)
+{
+	u32 status_value = 0x1;
+
+	while ((status_value & 0x1)==0x1)
+	{
+		qspi->ipcr = 3 << 24;
+		while(qspi->sr & 0x1);
+		while(!(qspi->sr & (1 << 16)));
+		status_value = QSPI_ARDB;
+		/* read complete */
+		qspi->fr = 0x10000;
+	}
+}
+
+void quadspi_init(void)
+{
+	quadspi_setup_clocks();
+
+	/* port configuration */
+	quadspi_setup_iomux();
+
+	quadspi_config();
+
+	quadspi_setup_lut();
+
+	/* set quad ddr as xbar read instruction  */
+	qspi->bfgencr = 0x9000;
+
+	/* set mdis bit  */
+	qspi->mcr = qspi->mcr | 0x4000;
+	/* for 33MHz clock  */
+	qspi->smpr = 0x10000;
+	/* clear mdis bit  */
+	qspi->mcr &= ~0x4000;
+
+	/* clear tx fifo */
+	qspi->mcr |= 0x800;
+
+	qspi->sfar = (qspidev ? QSPI1_FLASH_BASE_ADDR : QSPI0_FLASH_BASE_ADDR);
+	quadspi_enable_quadbit();
+	qspi->sfar = (qspidev ? QSPI1_FLASH_BASE_ADDR : QSPI0_FLASH_BASE_ADDR);
+}
+
+static void quadspi_enable_quadbit(void)
+{
+	/* write enable */
+	qspi->ipcr = 1 << 24;
+
+	while(qspi->sr & 0x1);
+
+	/* write data to Tx Buffer */
+	/* enable flash quad mode */
+	qspi->tbdr = 0x00020000;
+
+	/* send write command */
+	qspi->ipcr = 5 << 24;
+
+	while(qspi->sr & 0x1);
+	quadspi_wait_while_flash_busy();
+
+	/* Read config reg to ensure write was successful */
+	qspi->ipcr = 6 << 24;
+	while(qspi->sr & 0x1);
+	/* read complete */
+	qspi->fr = 0x10000;
+}
+
+void quadspi_erase(void)
+{
+	qspi->sfar = qspibase;
+
+	/*write enable*/
+	qspi->ipcr = 1 << 24;
+	while(qspi->sr & 0x1);
+
+	/*send erase command */
+	qspi->ipcr = 2 << 24;
+	while(qspi->sr & 0x1);
+
+	quadspi_wait_while_flash_busy();
+}
+
+void quadspi_erase_sector(unsigned int addr)
+{
+	debug ("Erasing QuadSPI flash addr=0x%x\n",addr);
+	qspi->sfar = addr;
+
+	/*write enable */
+	qspi->ipcr = 1 << 24;
+	while(qspi->sr & 0x1);
+
+	/*send erase sector command */
+	qspi->ipcr = 7 << 24;
+	while(qspi->sr & 0x1);
+
+	quadspi_wait_while_flash_busy();
+}
+
+void quadspi_program(unsigned int src, unsigned int base, unsigned int size)
+{
+	unsigned int *start_address = (unsigned int *)src;
+	unsigned int *end_address = (unsigned int *)(src + size);
+	unsigned int *page_address = start_address;
+	unsigned int *flash_address = (unsigned int *)base;
+	int page_size = QSPI_FLASH_PGSZ;
+	unsigned int *current_address = start_address;
+	unsigned int data_value;
+	int i;
+
+	/* 1024 offset for spansion */
+	qspi->sfar = (unsigned int)flash_address;
+	/* clear Tx fifo */
+	qspi->mcr |= 0x800;
+
+	page_address = start_address + (page_size >> 2);
+	do {
+		if ((unsigned int)flash_address % 0x10000 == 0)
+			quadspi_erase_sector((unsigned int)flash_address);
+
+
+		/* write enable  */
+		qspi->ipcr = 1 << 24;
+		while(qspi->sr & 0x1);
+		/* clear Tx fifo */
+		qspi->mcr |= 0x800;
+
+		while (current_address < page_address)
+		{
+			/* fill tx fifo (64 bytes) */
+			for (i = 0; i < 16; i++)
+			{
+			  data_value=*(current_address++);
+			  qspi->tbdr = __swap_32(data_value);
+			}
+			/*page program 256bytes  */
+			qspi->ipcr = (4 << 24) | page_size;
+			for (i = 0; i < 48; i++)
+			{
+				/* while TX fifo Full */
+				while(qspi->sr & 0x8000000u);
+				data_value=*(current_address++);
+				qspi->tbdr = __swap_32(data_value);
+			}
+			while(qspi->sr & 0x1);
+			quadspi_wait_while_flash_busy();
+
+		}
+		page_address += (page_size >> 2);
+		flash_address += (page_size >> 2);
+		qspi->sfar = (unsigned int)flash_address;
+	} while (current_address < end_address);
+}
+
+int quadspi_write_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong length = 1;
+	ulong dest, src;
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	 /* Address is specified since argc > 1 */
+	dest = simple_strtoul(argv[1], NULL, 16);
+
+	src = simple_strtoul(argv[2], NULL, 16);
+	length = simple_strtoul(argv[3], NULL, 16);
+
+	if (!src || !length)
+		return CMD_RET_USAGE;
+
+	/* Check if in the QSPI address range */
+	if (!((dest >= qspibase) && (dest + length <= qspi->sfb2ad)))
+		return CMD_RET_USAGE;
+
+	quadspi_program(src, dest, length);
+	print_buffer(dest, (void*)dest, 2, 0x10, 8);
+	return 0;
+
+}
+U_BOOT_CMD(
+        qspiwrite, 4, 0, quadspi_write_cmd,
+	"Write/programm the QSPI memory",
+        "qspiwrite destAddr srcAddr length\n"
+        "	destAddr: is an address in the QSPI domain\n"
+	"	srcAddr: is the source address\n"
+	"	length: size in bytes\n"
+	"	Example:\n"
+	"		qspiwrite 0x20000000 0x3f800000 0x1000\n"
+        ""
+);
+
+int quadspi_init_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int  addr;
+	int i;
+
+	if (argc < 2)
+                return CMD_RET_USAGE;
+	/* dev= must be first argument */
+	if (!strncmp(argv[1], "dev=", 4)) {
+		qspidev = simple_strtoul(argv[1] + 4, NULL, 16);
+		switch (qspidev) {
+		case 0:
+			qspi = (struct quadspi *)QSPI0_BASE_ADDR;
+			qspibase = QSPI0_FLASH_BASE_ADDR;
+		break;
+		case 1:
+			qspi =  (struct quadspi *)QSPI1_BASE_ADDR;
+			qspibase = QSPI1_FLASH_BASE_ADDR;
+		break;
+		default:
+			return CMD_RET_USAGE;
+		}
+	} else
+		return CMD_RET_USAGE;
+
+	for (i = 2; i < argc; i++) {
+		addr = simple_strtoul(argv[i] + 4, NULL, 16);
+		if (!strncmp(argv[i], "fa1=", 4)){
+			qspi->sfa1ad = addr;
+			/* assume there is no FA2 */
+			qspi->sfa2ad = addr;
+			/* assume there is no FB1 */
+			qspi->sfb1ad = addr;
+		} else if (!strncmp(argv[i], "fa2=", 4)) {
+			/* FA2 can only be set if FA1 is already set */
+			if (!qspi->sfa1ad)
+                                return CMD_RET_USAGE;
+			qspi->sfa2ad = addr;
+			/* assume there is no FB1 */
+                        qspi->sfb1ad = addr;
+		} else if (!strncmp(argv[i], "fb1=", 4)) {
+			/* FB1 can only be set if FA is already set */
+			if (!qspi->sfa1ad)
+				return CMD_RET_USAGE;
+			qspi->sfb1ad = addr;
+			/* assume there is no FB2 */
+			qspi->sfb2ad = addr;
+		} else if (!strncmp(argv[i], "fb2=", 4)) {
+			if (!qspi->sfb1ad || !qspi->sfa1ad)
+				return CMD_RET_USAGE;
+                        qspi->sfb2ad = addr;
+		} else
+			return CMD_RET_USAGE;
+	}
+
+	debug ("Init QuadSPI dev %d\n", qspidev);
+	quadspi_init();
+	return 0;
+}
+U_BOOT_CMD(
+        qspiinit, 4, 0, quadspi_init_cmd,
+        "initialize the QSPI",
+        "qspiiint dev=X <fa1=A1> <fa2=A2> <fb1=B1> <fb2=B2>\n"
+	"	dev= set 0 for qspi0 and 1 for qsp1\n"
+        "	fa1= is the address of the top flash A1 device\n"
+	"	fa2= is the address of the top flash A2 device\n"
+	"	fb1= is the address of the top flash B1 device\n"
+	"	fb2= is the address of the top flash B2 device\n"
+	" Note that fa1, fa2, fb1 and fb2 are optional but they must be listed\n "
+	" in that order, you can not list fb1 before fa1 for instance\n"
+	"	Example1:\n"
+	"	   Initialize QSPI0 using default values\n"
+	"		qspiinit dev=0\n"
+	"	Example2:\n"
+	"	   Set FA1 and FB1\n"
+	"		qspiinit dev=0 fa1=0x21000000 fb1=0x22000000\n"
+	""
+);