sh: MS7750SE support.

This adds support for the Hitachi MS7750SE.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Makefile

@@ -2408,6 +2408,18 @@ atstk1002_config	:	unconfig
 #########################################################################
 #########################################################################
 
+#########################################################################
+## sh4 (Renesas SuperH)
+#########################################################################
+ms7750se_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_MS7750SE 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 ms7750se
+
+#########################################################################
+#########################################################################
+#########################################################################
+
 clean:
 	find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \

board/ms7750se/Makefile

@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ms7750se.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################

board/ms7750se/config.mk

@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x8FFC0000

board/ms7750se/lowlevel_init.S

@@ -0,0 +1,169 @@
+/*
+	modified from SH-IPL+g
+	Renesaso SuperH Solution Enginge MS775x BSC setting 
+	Coyright (c) 2007 Nobuhiro Iwamatsu
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7751
+#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MRSHPC
+#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#else /* CONFIG_MRSHPC*/
+#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+#endif /* CONFIG_MRSHPC */
+#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define LED_ADDRESS	0xBA000000 /* Address of LED register */ 	
+#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#define SWITCH_ADDR	0xB9000000 /* Address of DIP switches */
+#else /* CONFIG_CPU_SUBTYPE_SH7751 */
+#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
+#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+				      A2: 1-3 A1: 1-3 A0: 0-1 */
+#define LED_ADDRESS	0xB0C00000 /* Address of LED register */ 	
+#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#define SWITCH_ADDR	0xb0800000 /* Address of DIP switches */
+#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
+
+	.global lowlevel_init
+	.text
+	.align  2
+
+lowlevel_init:
+
+	mov.l   L_CCR, r1               ! CCR Address
+	mov.l   L_CCR_DISABLE, r0       ! CCR Data
+	mov.l   r0, @r1
+
+init_bsc:
+	mov.l	FRQCR_A,r1	/* FRQCR Address */
+	mov.l	FRQCR_D,r0	/* FRQCR Data */
+	mov.w	r0,@r1
+
+	mov.l	BCR1_A,r1	/* BCR1 Address */
+	mov.l	BCR1_D,r0	/* BCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	BCR2_A,r1	/* BCR2 Address */
+	mov.l	BCR2_D,r0	/* BCR2 Data */
+	mov.w	r0,@r1
+
+	mov.l	WCR1_A,r1	/* WCR1 Address */
+	mov.l	WCR1_D,r0	/* WCR1 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR2_A,r1	/* WCR2 Address */
+	mov.l	WCR2_D,r0	/* WCR2 Data */
+	mov.l	r0,@r1
+
+	mov.l	WCR3_A,r1	/* WCR3 Address */
+	mov.l	WCR3_D,r0	/* WCR3 Data */
+	mov.l	r0,@r1
+
+	mov.l	LED_A,r1	/* LED Address */
+	mov	#0xff,r0	/* LED ALL 'on' */
+	shll8	r0
+	mov.w	r0,@r1
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D1,r0	/* MCR Data1 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	! Do you need PCMCIA setting?	
+	! If so, please add the lines here...
+
+	mov.l	RTCNT_A,r1	/* RTCNT Address */
+	mov.l	RTCNT_D,r0	/* RTCNT Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCOR_A,r1	/* RTCOR Address */
+	mov.l	RTCOR_D,r0	/* RTCOR Data */
+	mov.w	r0,@r1
+
+	mov.l	RTCSR_A,r1	/* RTCSR Address */
+	mov.l	RTCSR_D,r0	/* RTCSR Data */
+	mov.w	r0,@r1
+
+	mov.l	RFCR_A,r1	/* RFCR Address */
+	mov.l	RFCR_D,r0	/* RFCR Data */
+	mov.w	r0,@r1		/* Clear reflesh counter */
+	/* Wait DRAM refresh 30 times */
+	mov	#30,r3
+1:
+	mov.w	@r1,r0
+	extu.w	r0,r2
+	cmp/hi	r3,r2
+	bf	1b
+
+	mov.l	MCR_A,r1	/* MCR Address */
+	mov.l	MCR_D2,r0	/* MCR Data2 */
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	rts
+	 nop
+
+	.align	2
+
+L_CCR:          .long   CCR
+L_CCR_DISABLE:  .long   0x0808
+FRQCR_A:	.long	FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_SUBTYPE_SH_R
+		.long	0x00000e1a	/* 12:3:3 */
+#else
+#ifdef CONFIG_GOOD_SESH4
+		.long	0x00000e13	/* 6:2:1 */
+#else
+		.long	0x00000e23	/* 6:1:1 */
+#endif
+#endif	/* CONFIG_CPU_SUBTYPE_SH_R */
+
+BCR1_A:		.long	BCR1
+BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
+BCR2_A:		.long	BCR2
+BCR2_D:		.long	BCR2_D_VALUE	/* Bus width settings */
+WCR1_A:		.long	WCR1
+WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
+WCR2_A:		.long	WCR2
+WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
+WCR3_A:		.long	WCR3
+WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
+LED_A:		.long	LED_ADDRESS	/* LED Address */
+RTCSR_A:	.long	RTCSR	
+RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCNT_A:	.long	RTCNT
+RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCOR_A:	.long	RTCOR
+RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+SDMR3_A:	.long	SDMR3_ADDRESS
+MCR_A:		.long	MCR
+MCR_D1:		.long	MCR_D1_VALUE
+MCR_D2:		.long	MCR_D2_VALUE
+RFCR_A:		.long	RFCR
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+

board/ms7750se/ms7750se.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2007 
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+	puts("BOARD: SH7750 Solution Engine\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}

board/ms7750se/u-boot.lds

@@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+	   
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+	   
+	*/
+	. = 0x8C000000 + (64*1024*1024) - (256*1024);
+	
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+	
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .); 
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
+

include/configs/ms7750se.h

@@ -0,0 +1,75 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7750	1
+#define CONFIG_MS7750SE		1
+#define __LITTLE_ENDIAN__	1
+
+//#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_NET |CFG_CMD_PING)
+#define CONFIG_COMMANDS        	CONFIG_CMD_DFL & ~CFG_CMD_NET 
+
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_CONS_SCIF1	1
+#define BOARD_LATE_INIT		1
+
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS    	"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+#define CFG_SDRAM_BASE		(0x8C000000)
+#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CFG_LONGHELP		
+#define CFG_PROMPT		"=> "		
+#define CFG_CBSIZE		256	
+#define CFG_PBSIZE		256	
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		512	
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }		/* List of legal baudrate settings for this board */
+
+#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)	/* Address of u-boot image in Flash */
+#define CFG_MONITOR_LEN		(128 * 1024)	
+#define CFG_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+
+#define CFG_GBL_DATA_SIZE	(256)			/* size in bytes reserved for initial data */
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)	
+#define CFG_RX_ETH_BUFFER	(8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef  CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_BASE		(0xA1000000)
+#define CFG_MAX_FLASH_BANKS	(1)			/* Max number of 
+						 	 * Flash memory banks
+						 	 */
+#define CFG_MAX_FLASH_SECT	142
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define TMU_CLK_DIVIDER		4
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define	CFG_PLL_SETTLING_TIME	100		/* in us */
+
+#endif /* __CONFIG_H */