Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  Arm: re-introduce the MACH_TYPE_XXXXXX for EB_CPUX9K2 board
  arm: jadecpu: Readd MACH_TYPE_JADECPU
  at91: defined mach-types for otc570 board in board config file
  at91: defined mach-types for meesc board in board config file
  mx31pdk: Enable D and I caches
  ehci-mxc: remove incorrect comment
  README: Fix supported i.MX SoC list for CONFIG_MXC_SPI
  mx53: Turn off child clocks before reconfigure perclk_root
  qong: enable support for compressed images
  imx: imx31_phycore.h: fix checkpatch warnings
  vision2: Remove unused get_board_rev function
  mx53smd: Remove unused get_board_rev function
  mx53ard: Remove unused get_board_rev function
  mx53evk: Remove unused get_board_rev function
  mx53evk: Add RTC support
  mx53loco: Remove unused get_board_rev function
  mx53evk: Remove unneeded '1' from mx53evk.h
  OMAP3: mvblx: Initial support for mvBlueLYNX-X
  ARM: dig297: Define MACH_TYPE_OMAP3_CPS and CONFIG_MACH_TYPE
  omap3: mem: Move comments next to definitions
  omap3: mem: Clean-up whitespaces
  omap3: mem: Define and use common macros
  Davinci: ea20: added PREBOOT to configuration
  Davinci: ea20: added I2C support
  Davinci: ea20: added video support
  VIDEO: davinci: add framebuffer to da8xx
  ARM: Davinci: added missing registers to hardware.h
  Davinci: ea20: add gpios for LCD backlight control
  Davinci: ea20: add gpio for keeping power on in board_late_init
  Davinci: ea20: Add default U-Boot environment
  Davinci: ea20: Add early init to get early output from console
  Davinci: ea20: Add NAND support
  Davinci: ea20: set GPIOs to hold MII-Phy in reset and set UART0-Switch for console
  Davinci: ea20: set console on UART0
  arm, davinci: add cam_enc_4xx support
  arm926ejs, davinci: add missing spi defines for dm365
  arm926ejs, davinci: add cpuinfo for dm365
  arm, davinci: add lowlevel function for dm365 soc
  arm, davinci: add header files for dm365
  spl, nand: add 4bit HW ecc oob first nand_read_page function
  arm, davinci: add support for new spl framework
  spl: add option for adding post memory test to the SPL framework
  net, davinci_emac: make clock divider in MDIO control register configurable
  arm, usb, davinci: make USBPHY_CTL register configurable
  usb, davinci: add enable_vbus() weak function
  omap3evm: fix errors caused by multiple definitions
  omap3evm: Add (quick) configuration for NAND only
  omap3evm: Add (quick) configuration for MMC/SD only
  omap3evm: move common config options to new file
  omap3evm: Prepare to split configuration
  omap3evm: Reorder related config options
  omap/spl: actually enable the console
  davinci_emac: compilation fix, phy is array now
  omap3evm: Set environment variable 'ethaddr'
  arm, arm926: fix missing symbols in NAND_SPL mode
  arm, davinci: Add function lpsc_syncreset()
  arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD
  arm/km: portl2 environment address update to P1B
  arm/km: adapt bootcounter evaluation
  arm/km: enable jffs2 cmds
  arm/km: trigger reconfiguration for the Xilinx FPGA
  arm/km: add boardid and hwkey to kernel command line
  ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards
  netspace_v2: enable I2C EEPROM support
  netspace_v2: fix SDRAM configuration
  armada100: define CONFIG_SYS_CACHELINE_SIZE
  pantheon: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: define CONFIG_SYS_CACHELINE_SIZE
  kirkwood: drop empty asm-offsets.s file
  arm/km/mgcoge3un: enhance "waitforne" feature
  arm/km: add variable waitforne to mgcoge3un
  gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
  ARM: dreamplug: fix compilation
  ARM: DockStar: fix compilation
  ARM: netspace_v2: fix warnings
  am335x: Drop board_sysinfo struct
  am335x: Temporarily add MACH_TYPE define
  misc:pmic:samsung Enable PMIC driver at C210 Universal target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p UNIVERSAL C210 target
  dcache:s5p CONFIG_SYS_CACHELINE_SIZE added for s5p GONI target
  smdkv310: use macro for mmc data read function address
  smdkv310: use spl framework for mmc spl
  SMDKV310: use get_ram_size() to validate dram size
  SMDKV310: Initialize board id using CONFIG_MACH_TYPE
  ORIGEN : use absolute paths and fix tool naming
  ORIGEN : enable device tree support
  MX25: tx25: Fix building due to missing MACH_TYPE
  mx31: Add board support for HALE TT-01
  mx31: add ESD control registers
  mx31: define pins and init for UART2 and CSPI3
  MX35: add support for flea3 board
  MX51: vision2: add MACH_TYPE in config file
  vision2: Remove unused header file
  mx51evk: Remove unused get_board_rev function
  mx51evk: Remove unneeded '1' from mx51evk.h
  I2C: Fix mxc_i2c.c problem on imx31_phycore
  mx35pdk: Add RTC support
  mx51evk: Use GPIO API for configuring the IOMUX
  mx51evk: Add RTC support
  rtc: Make mc13783-rtc driver generic
  qong: remove unneeded IOMUX settings
  qong: Use mx31_set_gpr to setup USBH2 pins
  mx31: Introduce mx31_set_gpr function
  mx31pdk: Add MC13783 PMIC support
  qong: remove unneeded "1" from qong.h
  misc: pmic: fix regression in pmic_fsl.c (SPI)
  mx5 configs: CONFIG_PRIME should really be CONFIG_ETHPRIME
  MX35: Drop unnecessary prototypes from imx-regs.h
  I2C: added I2C-2 and I2C-3 to MX35
  MX35: factorize common assembly code
  MX35: add reset cause as provided by other i.MX
  MX35: add pins definition for UART3
  MX35: added ESDC structure to imx-regs

MAINTAINERS

@@ -421,6 +421,7 @@ Georg Schardt <schardt@team-ctech.de>
 
 Heiko Schocher <hs@denx.de>
 
+	cam_enc_4xx	davinci/ARM926EJS
 	charon		MPC5200
 	ids8247		MPC8247
 	jupiter		MPC5200
@@ -560,6 +561,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
 Stefano Babic <sbabic@denx.de>
 
 	ea20		davinci
+	flea3		i.MX35
 	mx35pdk		i.MX35
 	mx51evk		i.MX51
 	polaris		xscale/pxa
@@ -666,6 +668,10 @@ Grazvydas Ignotas <notasas@gmail.com>
 
 	omap3_pandora	ARM ARMV7 (OMAP3xx SoC)
 
+Michael Jones <michael.jones@matrix-vision.de>
+
+	omap3_mvblx	ARM ARMV7 (OMAP3xx SoC)
+
 Matthias Kaehlcke <matthias@kaehlcke.net>
 	edb9301			ARM920T (EP9301)
 	edb9302			ARM920T (EP9302)
@@ -757,6 +763,10 @@ Sandeep Paulraj <s-paulraj@ti.com>
 	davinci_dm365evm	ARM926EJS
 	davinci_dm6467evm	ARM926EJS
 
+Helmut Raiger <helmut.raiger@hale.at>
+
+	tt01		i.MX31
+
 Linus Walleij <linus.walleij@linaro.org>
 	integratorap	various
 	integratorcp	various

Makefile

@@ -416,9 +416,13 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot.ubl:       $(obj)u-boot-nand.bin
+$(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
 		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
+		rm $(obj)u-boot-ubl.bin
+		rm $(obj)spl/u-boot-spl-pad.bin
 
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \

README

@@ -876,7 +876,7 @@ The following options need to be configured:
 
 		CONFIG_RTC_MPC8xx	- use internal RTC of MPC8xx
 		CONFIG_RTC_PCF8563	- use Philips PCF8563 RTC
-		CONFIG_RTC_MC13783	- use MC13783 RTC
+		CONFIG_RTC_MC13XXX	- use MC13783 or MC13892 RTC
 		CONFIG_RTC_MC146818	- use MC146818 RTC
 		CONFIG_RTC_DS1307	- use Maxim, Inc. DS1307 RTC
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
@@ -1904,7 +1904,7 @@ The following options need to be configured:
 		CONFIG_MXC_SPI
 
 		Enables the driver for the SPI controllers on i.MX and MXC
-		SoCs. Currently only i.MX31 is supported.
+		SoCs. Currently i.MX31/35/51 are supported.
 
 - FPGA Support: CONFIG_FPGA
 
@@ -3257,6 +3257,11 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 
+- CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+		define this, if you want to read first the oob data
+		and then the data. This is used for example on
+		davinci plattforms.
+
 - CONFIG_USE_ARCH_MEMCPY
   CONFIG_USE_ARCH_MEMSET
 		If these options are used a optimized version of memcpy/memset will

arch/arm/cpu/arm1136/mx31/devices.c

@@ -38,7 +38,22 @@ void mx31_uart1_hw_init(void)
 }
 #endif
 
+#ifdef CONFIG_SYS_MX31_UART2
+void mx31_uart2_hw_init(void)
+{
+	/* setup pins for UART2 */
+	mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
+	mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
+}
+#endif
+
 #ifdef CONFIG_MXC_SPI
+/*
+ * Note: putting several spi setups here makes no sense as they may differ
+ * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
+ */
 void mx31_spi2_hw_init(void)
 {
 	/* SPI2 */

arch/arm/cpu/arm1136/mx31/generic.c

@@ -27,6 +27,8 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
+#define IOMUXGPR	(IOMUXC_BASE + 0x008)
+
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = GET_PLL_MFI(reg);
@@ -141,6 +143,19 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 
 }
 
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+	u32 l;
+
+	l = readl(IOMUXGPR);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, IOMUXGPR);
+}
+
 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
 {
 	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;

arch/arm/cpu/arm1136/mx35/generic.c

@@ -422,12 +422,39 @@ U_BOOT_CMD(
 	""
 );
 
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0002:
+		return "JTAG";
+	case 0x0004:
+		return "RST";
+	case 0x0008:
+		return "WDOG";
+	default:
+		return "unknown reset";
+	}
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	printf("CPU:   Freescale i.MX35 at %d MHz\n",
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
+		(srev & 0xF0) >> 4, (srev & 0x0F),
 		get_mcu_main_clk() / 1000000);
-	/* mxc_dump_clocks(); */
+
+	printf("Reset cause: %s\n", get_reset_cause());
+
 	return 0;
 }
 #endif

arch/arm/cpu/arm926ejs/davinci/Makefile

@@ -35,6 +35,11 @@ COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_SOC_DM646X)	+= dm646x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o
+COBJS-y	+= dm365_lowlevel.o
+endif
+
 SOBJS	= reset.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT

arch/arm/cpu/arm926ejs/davinci/cpu.c

@@ -146,13 +146,15 @@ static inline unsigned pll_prediv(volatile void *pllbase)
 		return 8;
 	else
 		return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+	return pll_div(pllbase, PLLC_PREDIV);
 #endif
 	return 1;
 }
 
 static inline unsigned pll_postdiv(volatile void *pllbase)
 {
-#ifdef CONFIG_SOC_DM355
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
 	return pll_div(pllbase, PLLC_POSTDIV);
 #elif defined(CONFIG_SOC_DM6446)
 	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
@@ -171,9 +173,13 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 #endif
 
 	/* the PLL might be bypassed */
-	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
 		base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
 		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
 		base /= pll_postdiv(pllbase);
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
@@ -184,8 +190,13 @@ int print_cpuinfo(void)
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
+#if defined(CONFIG_SOC_DM365)
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
 	printf("Cores: ARM %d MHz",
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
 
 #ifdef DSP_PLLDIV
 	printf(", DSP %d MHz",
@@ -194,8 +205,13 @@ int print_cpuinfo(void)
 
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+				/ 2);
+#else
 			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
 				/ 2);
+#endif
 	return 0;
 }
 
@@ -205,6 +221,13 @@ unsigned int davinci_arm_clk_get()
 	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
 }
 #endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
 #endif /* CONFIG_DISPLAY_CPUINFO */
 #endif /* !CONFIG_SOC_DA8XX */
 

arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c

@@ -0,0 +1,439 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+	unsigned long	i;
+
+	for (i = 0; i < loopcnt; i++)
+		asm("   NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(150);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/*Bring PLL out of Reset*/
+	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL1 */
+	writel(pllmult, &dv_pll0_regs->pllm);
+	writel(prediv, &dv_pll0_regs->prediv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+	/* Program the PostDiv for PLL1 */
+	writel(0x8000, &dv_pll0_regs->postdiv);
+
+	/* Post divider setting for PLL1 */
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+	dm365_waitloop(300);
+
+	/* Set the GOSET bit */
+	writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+	dm365_waitloop(300);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+		== PLL0_LOCK))
+		;
+
+	/* Enable the PLL Bit of PLLCTL*/
+	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+	return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+	unsigned int clksrc = 0x0;
+
+	/* Power up the PLL*/
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+	/*
+	 * Select the Clock Mode as Onchip Oscilator or External Clock on
+	 * MXI pin
+	 * VDB has input on MXI pin
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+	setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8);
+
+	/*
+	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+	 * through MMR
+	 */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+	/* Set PLLEN=0 => PLL BYPASS MODE */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	dm365_waitloop(50);
+
+	 /* PLLRST=1(reset assert) */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	dm365_waitloop(300);
+
+	/* Bring PLL out of Reset */
+	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+	/* Program the Multiper and Pre-Divider for PLL2 */
+	writel(pllm, &dv_pll1_regs->pllm);
+	writel(prediv, &dv_pll1_regs->prediv);
+
+	writel(0x8000, &dv_pll1_regs->postdiv);
+
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+		PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+		&dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+	writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+	/* Post divider setting for PLL2 */
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+	/* GoCmd for PostDivider to take effect */
+	writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+	dm365_waitloop(150);
+
+	/* Wait for PLL to LOCK */
+	while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+		== PLL1_LOCK))
+		;
+
+	dm365_waitloop(4100);
+
+	/* Enable the PLL2 */
+	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+	/* do this after PLL's have been set up */
+	writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+		&dv_sys_module_regs->peri_clkctl);
+
+	return 0;
+}
+
+int dm365_ddr_setup(void)
+{
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+	clrbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+	/* Set bit CLRZ (bit 13) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+	/* Check VTP READY Status */
+	while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+		;
+
+	/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+	/* Set bit LOCK(bit7) */
+	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+	/*
+	 * Powerdown VTP as it is locked (bit 6)
+	 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+	 */
+	setbits_le32(&dv_sys_module_regs->vtpiocr,
+		VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+	/* Wait for calibration to complete */
+	dm365_waitloop(150);
+
+	/* Set the DDR2 to synreset, then enable it again */
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+	/* Program SDRAM Bank Config Register */
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+		&dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Timing Control Register1 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+	/* Program SDRAM Timing Control Register2 */
+	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+	writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+	writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+	/* Program SDRAM Refresh Control Register */
+	writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+	return 0;
+}
+
+void dm365_vpss_sync_reset(void)
+{
+	unsigned int PdNum = 0;
+
+	/* VPSS_CLKMD 1:1 */
+	setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+		VPSS_CLK_CTL_VPSS_CLKMD);
+
+	/* LPSC SyncReset DDR Clock Enable */
+	writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) |
+		PSC_SYNCRESET), &dv_psc_regs->mdctl[47]);
+
+	writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+	while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+		;
+	while (!((readl(&dv_psc_regs->mdstat[47]) &  PSC_MD_STATE_MSK) ==
+		PSC_SYNCRESET))
+		;
+}
+
+void dm365_por_reset(void)
+{
+	if (readl(&dv_pll0_regs->rstype) & 3)
+		dm365_vpss_sync_reset();
+}
+
+void dm365_psc_init(void)
+{
+	unsigned char i = 0;
+	unsigned char lpsc_start;
+	unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+	unsigned int  PdNum = 0;
+
+	lpscmin = 0;
+	lpscmax = 2;
+
+	for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+		if (lpscgroup == 0) {
+			lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */
+			lpsc_end   = 28;
+		} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+			lpsc_start = 38;
+			lpsc_end   = 47;
+		} else {
+			lpsc_start = 50;
+			lpsc_end   = 51;
+		}
+
+		/* NEXT=0x3, Enable LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			setbits_le32(&dv_psc_regs->mdctl[i], 0x3);
+
+		/*
+		 * Program goctl to start transition sequence for LPSCs
+		 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+		 * Domain 0 Modules
+		 */
+		writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+		/*
+		 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+		 */
+		while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+			== 0))
+			;
+
+		/* Wait for MODSTAT = ENABLE from LPSC's */
+		for (i = lpsc_start; i <= lpsc_end; i++)
+			while (!((readl(&dv_psc_regs->mdstat[i]) &
+				PSC_MD_STATE_MSK) == 0x3))
+				;
+	}
+}
+
+static void dm365_emif_init(void)
+{
+	writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+	writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+	setbits_le32(&davinci_emif_regs->nandfcr, 1);
+
+	writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+	return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value)
+{
+	clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+	setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+	return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+	return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+	/*
+	 * copied from arch/arm/cpu/arm926ejs/start.S
+	 *
+	 * flush v4 I/D caches
+	 */
+	asm("mov	r0, #0");
+	asm("mcr	p15, 0, r0, c7, c7, 0");	/* flush v3/v4 cache */
+	asm("mcr	p15, 0, r0, c8, c7, 0");	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	asm("mrc	p15, 0, r0, c1, c0, 0");
+	/* clear bits 13, 9:8 (--V- --RS) */
+	asm("bic	r0, r0, #0x00002300");
+	/* clear bits 7, 2:0 (B--- -CAM) */
+	asm("bic	r0, r0, #0x00000087");
+	/* set bit 2 (A) Align */
+	asm("orr	r0, r0, #0x00000002");
+	/* set bit 12 (I) I-Cache */
+	asm("orr	r0, r0, #0x00001000");
+	asm("mcr	p15, 0, r0, c1, c0, 0");
+
+	/* Mask all interrupts */
+	writel(0x04, &dv_aintc_regs->intctl);
+	writel(0x0, &dv_aintc_regs->eabase);
+	writel(0x0, &dv_aintc_regs->eint0);
+	writel(0x0, &dv_aintc_regs->eint1);
+
+	/* Clear all interrupts */
+	writel(0xffffffff, &dv_aintc_regs->fiq0);
+	writel(0xffffffff, &dv_aintc_regs->fiq1);
+	writel(0xffffffff, &dv_aintc_regs->irq0);
+	writel(0xffffffff, &dv_aintc_regs->irq1);
+
+	/* System PSC setup - enable all */
+	dm365_psc_init();
+
+	/* Setup Pinmux */
+	dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+	dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+	dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+	dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+	dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+	/* PLL setup */
+	dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+		CONFIG_SYS_DM36x_PLL1_PREDIV);
+	dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+		CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+	/*
+	 * Fix Power and Emulation Management Register
+	 * see sprufh2.pdf page 38 Table 22
+	 */
+	writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30));
+	puts("ddr init\n");
+	dm365_ddr_setup();
+
+	puts("emif init\n");
+	dm365_emif_init();
+
+#if defined(CONFIG_POST)
+	/*
+	 * Do memory tests, calls arch_memory_failure_handle()
+	 * if error detected.
+	 */
+	memory_post_test(0);
+#endif
+}

arch/arm/cpu/arm926ejs/davinci/psc.c

@@ -46,7 +46,7 @@
  */
 
 /* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
+static void lpsc_transition(unsigned int id, unsigned int state)
 {
 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
 #ifdef CONFIG_SOC_DA8XX
@@ -83,10 +83,10 @@ void lpsc_on(unsigned int id)
 	while (readl(ptstat) & 0x01)
 		continue;
 
-	if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
-		return; /* Already on and enabled */
+	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+		return; /* Already in that state */
 
-	writel(readl(mdctl) | 0x03, mdctl);
+	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
 
 	switch (id) {
 #ifdef CONFIG_SOC_DM644X
@@ -114,10 +114,20 @@ void lpsc_on(unsigned int id)
 
 	while (readl(ptstat) & 0x01)
 		continue;
-	while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
+	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
 		continue;
 }
 
+void lpsc_on(unsigned int id)
+{
+	lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+	lpsc_transition(id, 0x01);
+}
+
 /* Not all DaVinci chips have a DSP power domain. */
 #ifdef CONFIG_SOC_DM644X
 

arch/arm/cpu/arm926ejs/davinci/spl.c

@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	dm36x_lowlevel_init(0);
+	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+
+	nand_init();
+	puts("Nand boot...\n");
+	nand_boot();
+}

arch/arm/cpu/arm926ejs/start.S

@@ -126,7 +126,15 @@ _fiq:
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
 	.word	CONFIG_SYS_TEXT_BASE
+#else
+#ifdef CONFIG_SPL_BUILD
+	.word	CONFIG_SPL_TEXT_BASE
+#else
+	.word	CONFIG_SYS_TEXT_BASE
+#endif
+#endif
 
 /*
  * These are defined in the board-specific linker script.
@@ -146,6 +154,12 @@ _bss_end_ofs:
 _end_ofs:
 	.word _end - _start
 
+#ifdef CONFIG_NAND_U_BOOT
+.globl _end
+_end:
+	.word __bss_end__
+#endif
+
 #ifdef CONFIG_USE_IRQ
 /* IRQ stack memory (calculated at run-time) */
 .globl IRQ_STACK_START
@@ -186,7 +200,15 @@ reset:
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
+#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
+	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#else
+#ifdef CONFIG_SPL_BUILD
+	ldr	sp, =(CONFIG_SPL_STACK)
+#else
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 	ldr	r0,=0x00000000
 	bl	board_init_f
@@ -211,6 +233,7 @@ stack_setup:
 	mov	sp, r4
 
 	adr	r0, _start
+	sub	r9, r6, r0		/* r9 <- relocation offset */
 	cmp	r0, r6
 	beq	clear_bss		/* skip relocation */
 	mov	r1, r6			/* r1 <- scratch for copy loop */
@@ -265,12 +288,17 @@ fixnext:
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+	/* No relocation for SPL */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end__
+#else
 	ldr	r0, _bss_start_ofs
 	ldr	r1, _bss_end_ofs
 	mov	r4, r6			/* reloc addr */
 	add	r0, r0, r4
 	add	r1, r1, r4
+#endif
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
@@ -278,6 +306,7 @@ clbss_l:str	r2, [r0]		/* clear loop...		    */
 	cmp	r0, r1
 	bne	clbss_l
 
+#ifndef CONFIG_SPL_BUILD
 	bl coloured_LED_init
 	bl red_led_on
 #endif

arch/arm/cpu/armv7/mx5/lowlevel_init.S

@@ -180,6 +180,21 @@
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
 	cmp r1, #0x0
 	bne 1b
+#else
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
 #endif
 
 	/* Switch ARM to step clock */

arch/arm/cpu/armv7/omap-common/spl.c

@@ -156,6 +156,8 @@ void preloader_console_init(void)
 
 	serial_init();		/* serial communications setup */
 
+	gd->have_console = 1;
+
 	/* Avoid a second "U-Boot" coming from this string */
 	u_boot_rev = &u_boot_rev[7];
 

arch/arm/include/asm/arch-am33xx/sys_proto.h

@@ -20,13 +20,6 @@
 #define _SYS_PROTO_H_
 
 #define BOARD_REV_ID	0x0
-struct {
-	u32 board_type_v1;
-	u32 board_type_v2;
-	u32 mtype;
-	char *board_string;
-	char *nand_string;
-} board_sysinfo;
 
 u32 get_cpu_rev(void);
 u32 get_sysboot_value(void);

arch/arm/include/asm/arch-armada100/config.h

@@ -33,6 +33,8 @@
 
 #include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */

arch/arm/include/asm/arch-davinci/aintc_defs.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_AINTC_DEFS_H_
+#define _DV_AINTC_DEFS_H_
+
+struct dv_aintc_regs {
+	unsigned int	fiq0;		/* 0x00 */
+	unsigned int	fiq1;		/* 0x04 */
+	unsigned int	irq0;		/* 0x08 */
+	unsigned int	irq1;		/* 0x0c */
+	unsigned int	fiqentry;	/* 0x10 */
+	unsigned int	irqentry;	/* 0x14 */
+	unsigned int	eint0;		/* 0x18 */
+	unsigned int	eint1;		/* 0x1c */
+	unsigned int	intctl;		/* 0x20 */
+	unsigned int	eabase;		/* 0x24 */
+	unsigned char	rsvd0[8];	/* 0x28 */
+	unsigned int	intpri0;	/* 0x30 */
+	unsigned int	intpri1;	/* 0x34 */
+	unsigned int	intpri2;	/* 0x38 */
+	unsigned int	intpri3;	/* 0x3c */
+	unsigned int	intpri4;	/* 0x40 */
+	unsigned int	intpri5;	/* 0x44 */
+	unsigned int	intpri6;	/* 0x48 */
+	unsigned int	intpri7;	/* 0x4c */
+};
+
+#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+
+#endif /* _DV_AINTC_DEFS_H_ */

arch/arm/include/asm/arch-davinci/da8xx-fb.h

@@ -0,0 +1,126 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+	QVGA = 0
+};
+
+enum panel_shade {
+	MONOCHROME = 0,
+	COLOR_ACTIVE,
+	COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+	LOAD_DATA = 1,
+	LOAD_PALETTE,
+};
+
+struct display_panel {
+	enum panel_type panel_type; /* QVGA */
+	int max_bpp;
+	int min_bpp;
+	enum panel_shade panel_shade;
+};
+
+struct da8xx_panel {
+	const char	name[25];	/* Full name <vendor>_<model> */
+	unsigned short	width;
+	unsigned short	height;
+	int		hfp;		/* Horizontal front porch */
+	int		hbp;		/* Horizontal back porch */
+	int		hsw;		/* Horizontal Sync Pulse Width */
+	int		vfp;		/* Vertical front porch */
+	int		vbp;		/* Vertical back porch */
+	int		vsw;		/* Vertical Sync Pulse Width */
+	unsigned int	pxl_clk;	/* Pixel clock */
+	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
+};
+
+struct da8xx_lcdc_platform_data {
+	const char manu_name[10];
+	void *controller_data;
+	const char type[25];
+	void (*panel_power_ctrl)(int);
+};
+
+struct lcd_ctrl_config {
+	const struct display_panel *p_disp_panel;
+
+	/* AC Bias Pin Frequency */
+	int ac_bias;
+
+	/* AC Bias Pin Transitions per Interrupt */
+	int ac_bias_intrpt;
+
+	/* DMA burst size */
+	int dma_burst_sz;
+
+	/* Bits per pixel */
+	int bpp;
+
+	/* FIFO DMA Request Delay */
+	int fdd;
+
+	/* TFT Alternative Signal Mapping (Only for active) */
+	unsigned char tft_alt_mode;
+
+	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+	unsigned char stn_565_mode;
+
+	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+	unsigned char mono_8bit_mode;
+
+	/* Invert line clock */
+	unsigned char invert_line_clock;
+
+	/* Invert frame clock  */
+	unsigned char invert_frm_clock;
+
+	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+	unsigned char sync_edge;
+
+	/* Horizontal and Vertical Sync: Control: 0=ignore */
+	unsigned char sync_ctrl;
+
+	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+	unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+	int back_porch;
+	int front_porch;
+	int pulse_width;
+};
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+
+#endif  /* ifndef DA8XX_FB_H */
+

arch/arm/include/asm/arch-davinci/dm365_lowlevel.h

@@ -0,0 +1,41 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __DM365_LOWLEVEL_H
+#define __DM365_LOWLEVEL_H
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void dm365_waitloop(unsigned long loopcnt);
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
+int dm365_ddr_setup(void);
+void dm365_por_reset(void);
+void dm365_psc_init(void);
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+	unsigned long value);
+void dm36x_lowlevel_init(ulong bootflag);
+
+#endif /* #ifndef __DM365_LOWLEVEL_H */

arch/arm/include/asm/arch-davinci/hardware.h

@@ -56,6 +56,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
 #define DAVINCI_UART0_BASE			(0x01c20000)
 #define DAVINCI_UART1_BASE			(0x01c20400)
+#define DAVINCI_TIMER3_BASE			(0x01c20800)
 #define DAVINCI_I2C_BASE			(0x01c21000)
 #define DAVINCI_TIMER0_BASE			(0x01c21400)
 #define DAVINCI_TIMER1_BASE			(0x01c21800)
@@ -63,6 +64,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_PWM0_BASE			(0x01c22000)
 #define DAVINCI_PWM1_BASE			(0x01c22400)
 #define DAVINCI_PWM2_BASE			(0x01c22800)
+#define DAVINCI_TIMER4_BASE			(0x01c23800)
 #define DAVINCI_SYSTEM_MODULE_BASE		(0x01c40000)
 #define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
 #define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
@@ -108,6 +110,9 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_MMC_SD1_BASE			0x01d00000
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
 #define DAVINCI_MMC_SD0_BASE			0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE		0x20000000
+#define DAVINCI_SPI0_BASE			0x01c66000
+#define DAVINCI_SPI1_BASE			0x01c66800
 
 #elif defined(CONFIG_SOC_DM646X)
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
@@ -157,6 +162,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_DDR_EMIF_DATA_BASE		0xc0000000
 #define DAVINCI_INTC_BASE			0xfffee000
 #define DAVINCI_BOOTCFG_BASE			0x01c14000
+#define DAVINCI_LCD_CNTL_BASE			0x01e13000
 #define DAVINCI_L3CBARAM_BASE			0x80000000
 #define JTAG_ID_REG                            (DAVINCI_BOOTCFG_BASE + 0x18)
 #define CHIP_REV_ID_REG				(DAVINCI_BOOTCFG_BASE + 0x24)
@@ -171,6 +177,10 @@ typedef volatile unsigned int *	dv_reg_p;
 #define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
 #define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
 #define GPIO_BANK2_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x44)
+#define GPIO_BANK6_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x88)
+#define GPIO_BANK6_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x8c)
+#define GPIO_BANK6_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x90)
+#define GPIO_BANK6_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x94)
 #endif /* CONFIG_SOC_DA8XX */
 
 /* Power and Sleep Controller (PSC) Domains */
@@ -292,6 +302,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #endif /* CONFIG_SOC_DA8XX */
 
 void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
 void dsp_on(void);
 
 void davinci_enable_uart0(void);
@@ -358,6 +369,7 @@ struct davinci_psc_regs {
 #endif /* CONFIG_SOC_DA8XX */
 
 #define PSC_MDSTAT_STATE		0x3f
+#define PSC_MDCTL_NEXT			0x07
 
 #ifndef CONFIG_SOC_DA8XX
 
@@ -434,7 +446,8 @@ struct davinci_syscfg_regs {
 	dv_reg	rsvd[13];
 	dv_reg	kick0;
 	dv_reg	kick1;
-	dv_reg	rsvd1[56];
+	dv_reg	rsvd1[53];
+	dv_reg	mstpri[3];
 	dv_reg	pinmux[20];
 	dv_reg	suspsrc;
 	dv_reg	chipsig;
@@ -454,7 +467,7 @@ struct davinci_syscfg_regs {
 #define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_UART0		(1 << 18)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
 
 struct davinci_syscfg1_regs {
@@ -541,4 +554,14 @@ static inline int get_async3_src(void)
 
 #endif /* CONFIG_SOC_DA8XX */
 
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+#endif
 #endif /* __ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-davinci/pll_defs.h

@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PLL_DEFS_H_
+#define _DV_PLL_DEFS_H_
+
+struct dv_pll_regs {
+	unsigned int	pid;		/* 0x00 */
+	unsigned char	rsvd0[224];	/* 0x04 */
+	unsigned int	rstype;		/* 0xe4 */
+	unsigned char	rsvd1[24];	/* 0xe8 */
+	unsigned int	pllctl;		/* 0x100 */
+	unsigned char	rsvd2[4];	/* 0x104 */
+	unsigned int	secctl;		/* 0x108 */
+	unsigned int	rv;		/* 0x10c */
+	unsigned int	pllm;		/* 0x110 */
+	unsigned int	prediv;		/* 0x114 */
+	unsigned int	plldiv1;	/* 0x118 */
+	unsigned int	plldiv2;	/* 0x11c */
+	unsigned int	plldiv3;	/* 0x120 */
+	unsigned int	oscdiv1;	/* 0x124 */
+	unsigned int	postdiv;	/* 0x128 */
+	unsigned int	bpdiv;		/* 0x12c */
+	unsigned char	rsvd5[8];	/* 0x130 */
+	unsigned int	pllcmd;		/* 0x138 */
+	unsigned int	pllstat;	/* 0x13c */
+	unsigned int	alnctl;		/* 0x140 */
+	unsigned int	dchange;	/* 0x144 */
+	unsigned int	cken;		/* 0x148 */
+	unsigned int	ckstat;		/* 0x14c */
+	unsigned int	systat;		/* 0x150 */
+	unsigned char	rsvd6[12];	/* 0x154 */
+	unsigned int	plldiv4;	/* 0x160 */
+	unsigned int	plldiv5;	/* 0x164 */
+	unsigned int	plldiv6;	/* 0x168 */
+	unsigned int	plldiv7;	/* 0x16C */
+	unsigned int	plldiv8;	/* 0x170 */
+	unsigned int	plldiv9;	/* 0x174 */
+};
+
+#define PLLCTL_PLLEN	(1 << 0)
+#define PLLCTL_PLLPWRDN	(1 << 1)
+#define PLLCTL_PLLRST	(1 << 3)
+#define PLLCTL_PLLENSRC	(1 << 5)
+#define PLLCTL_RES_9	(1 << 8)
+
+#define PLLSECCTL_TINITZ	(1 << 16)
+#define PLLSECCTL_TENABLE	(1 << 17)
+#define PLLSECCTL_TENABLEDIV	(1 << 18)
+#define PLLSECCTL_STOPMODE	(1 << 22)
+
+#define PLLCMD_GOSET		(1 << 0)
+
+#define PLL0_LOCK		0x07000000
+#define PLL1_LOCK		0x07000000
+
+#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+
+#define ARM_PLLDIV	(offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV	(offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV	(offsetof(struct dv_pll_regs, plldiv4))
+
+unsigned int davinci_clk_get(unsigned int div);
+#endif /* _DV_PLL_DEFS_H_ */

arch/arm/include/asm/arch-davinci/psc_defs.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_PSC_DEFS_H_
+#define _DV_PSC_DEFS_H_
+
+/*
+ * Power/Sleep Ctrl Register structure
+ * See sprufb3.pdf, Chapter 7
+ */
+struct dv_psc_regs {
+	unsigned int	pid;		/* 0x000 */
+	unsigned char	rsvd0[16];	/* 0x004 */
+	unsigned char	rsvd1[4];	/* 0x014 */
+	unsigned int	inteval;	/* 0x018 */
+	unsigned char	rsvd2[36];	/* 0x01C */
+	unsigned int	merrpr0;	/* 0x040 */
+	unsigned int	merrpr1;	/* 0x044 */
+	unsigned char	rsvd3[8];	/* 0x048 */
+	unsigned int	merrcr0;	/* 0x050 */
+	unsigned int	merrcr1;	/* 0x054 */
+	unsigned char	rsvd4[8];	/* 0x058 */
+	unsigned int	perrpr;		/* 0x060 */
+	unsigned char	rsvd5[4];	/* 0x064 */
+	unsigned int	perrcr;		/* 0x068 */
+	unsigned char	rsvd6[4];	/* 0x06C */
+	unsigned int	epcpr;		/* 0x070 */
+	unsigned char	rsvd7[4];	/* 0x074 */
+	unsigned int	epccr;		/* 0x078 */
+	unsigned char	rsvd8[144];	/* 0x07C */
+	unsigned char	rsvd9[20];	/* 0x10C */
+	unsigned int	ptcmd;		/* 0x120 */
+	unsigned char	rsvd10[4];	/* 0x124 */
+	unsigned int	ptstat;		/* 0x128 */
+	unsigned char	rsvd11[212];	/* 0x12C */
+	unsigned int	pdstat0;	/* 0x200 */
+	unsigned int	pdstat1;	/* 0x204 */
+	unsigned char	rsvd12[248];	/* 0x208 */
+	unsigned int	pdctl0;		/* 0x300 */
+	unsigned int	pdctl1;		/* 0x304 */
+	unsigned char	rsvd13[536];	/* 0x308 */
+	unsigned int	mckout0;	/* 0x520 */
+	unsigned int	mckout1;	/* 0x524 */
+	unsigned char	rsvd14[728];	/* 0x528 */
+	unsigned int	mdstat[52];	/* 0x800 */
+	unsigned char	rsvd15[304];	/* 0x8D0 */
+	unsigned int	mdctl[52];	/* 0xA00 */
+};
+
+/* PSC constants */
+#define EMURSTIE_MASK	(0x00000200)
+
+#define PD0		(0)
+
+#define PSC_ENABLE		(0x3)
+#define PSC_DISABLE		(0x2)
+#define PSC_SYNCRESET		(0x1)
+#define PSC_SWRSTDISABLE	(0x0)
+
+#define PSC_GOSTAT		(1 << 0)
+#define PSC_MD_STATE_MSK	(0x1f)
+
+#define PSC_CMD_GO		(1 << 0)
+
+#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
+
+#endif /* _DV_PSC_DEFS_H_ */

arch/arm/include/asm/arch-davinci/syscfg_defs.h

@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DV_SYSCFG_DEFS_H_
+#define _DV_SYSCFG_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+/* System Control Module register structure for DM365 */
+struct dv_sys_module_regs {
+	unsigned int	pinmux[5];	/* 0x00 */
+	unsigned int	bootcfg;	/* 0x14 */
+	unsigned int	arm_intmux;	/* 0x18 */
+	unsigned int	edma_evtmux;	/* 0x1C */
+	unsigned int	ddr_slew;	/* 0x20 */
+	unsigned int	clkout;		/* 0x24 */
+	unsigned int	device_id;	/* 0x28 */
+	unsigned int	vdac_config;	/* 0x2C */
+	unsigned int	timer64_ctl;	/* 0x30 */
+	unsigned int	usbbphy_ctl;	/* 0x34 */
+	unsigned int	misc;		/* 0x38 */
+	unsigned int	mstpri[2];	/* 0x3C */
+	unsigned int	vpss_clkctl;	/* 0x44 */
+	unsigned int	peri_clkctl;	/* 0x48 */
+	unsigned int	deepsleep;	/* 0x4C */
+	unsigned int	dft_enable;	/* 0x50 */
+	unsigned int	debounce[8];	/* 0x54 */
+	unsigned int	vtpiocr;	/* 0x74 */
+	unsigned int	pupdctl0;	/* 0x78 */
+	unsigned int	pupdctl1;	/* 0x7C */
+	unsigned int	hdimcopbt;	/* 0x80 */
+	unsigned int	pll0_config;	/* 0x84 */
+	unsigned int	pll1_config;	/* 0x88 */
+};
+
+#define VPTIO_RDY	(1 << 15)
+#define VPTIO_IOPWRDN	(1 << 14)
+#define VPTIO_CLRZ	(1 << 13)
+#define VPTIO_LOCK	(1 << 7)
+#define VPTIO_PWRDN	(1 << 6)
+
+#define VPSS_CLK_CTL_VPSS_CLKMD	(1 << 7)
+
+#define dv_sys_module_regs \
+	((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
+
+#endif /* !CONFIG_SOC_DA8XX */
+#endif /* _DV_SYSCFG_DEFS_H_ */

arch/arm/include/asm/arch-kirkwood/config.h

@@ -41,7 +41,8 @@
 
 #include <asm/arch/kirkwood.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
-
+#define CONFIG_SYS_CACHELINE_SIZE	32
+				/* default Dcache Line length for kirkwood */
 #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */

arch/arm/include/asm/arch-mx31/clock.h

@@ -37,8 +37,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk);
 extern u32 imx_get_uartclk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 extern void mx31_set_pad(enum iomux_pins pin, u32 config);
+extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
 
 void mx31_uart1_hw_init(void);
+void mx31_uart2_hw_init(void);
 void mx31_spi2_hw_init(void);
 void mxc_hw_watchdog_enable(void);
 void mxc_hw_watchdog_reset(void);

arch/arm/include/asm/arch-mx31/imx-regs.h

@@ -468,6 +468,44 @@ enum iomux_pins {
 	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
 };
 
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+	MUX_PGP_FIRI			= 1 << 0,
+	MUX_DDR_MODE			= 1 << 1,
+	MUX_PGP_CSPI_BB			= 1 << 2,
+	MUX_PGP_ATA_1			= 1 << 3,
+	MUX_PGP_ATA_2			= 1 << 4,
+	MUX_PGP_ATA_3			= 1 << 5,
+	MUX_PGP_ATA_4			= 1 << 6,
+	MUX_PGP_ATA_5			= 1 << 7,
+	MUX_PGP_ATA_6			= 1 << 8,
+	MUX_PGP_ATA_7			= 1 << 9,
+	MUX_PGP_ATA_8			= 1 << 10,
+	MUX_PGP_UH2			= 1 << 11,
+	MUX_SDCTL_CSD0_SEL		= 1 << 12,
+	MUX_SDCTL_CSD1_SEL		= 1 << 13,
+	MUX_CSPI1_UART3			= 1 << 14,
+	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
+	MUX_TAMPER_DETECT_EN		= 1 << 16,
+	MUX_PGP_USB_4WIRE		= 1 << 17,
+	MUX_PGP_USB_COMMON		= 1 << 18,
+	MUX_SDHC_MEMSTICK1		= 1 << 19,
+	MUX_SDHC_MEMSTICK2		= 1 << 20,
+	MUX_PGP_SPLL_BYP		= 1 << 21,
+	MUX_PGP_UPLL_BYP		= 1 << 22,
+	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
+	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
+	MUX_CSPI3_UART5_SEL		= 1 << 25,
+	MUX_PGP_ATA_9			= 1 << 26,
+	MUX_PGP_USB_SUSPEND		= 1 << 27,
+	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
+	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
+	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
+	MUX_CLKO_DDR_MODE		= 1 << 31,
+};
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B	(1 << 31)
 #define CCM_RCSR_NFMS	(1 << 30)
@@ -484,6 +522,17 @@ struct mx31_weim {
 	struct mx31_weim_cscr cscr[6];
 };
 
+/* ESD control registers */
+struct esdc_regs {
+	u32 ctl0;
+	u32 cfg0;
+	u32 ctl1;
+	u32 cfg1;
+	u32 misc;
+	u32 dly[5];
+	u32 dlyl;
+};
+
 #endif
 
 #define __REG(x)     (*((volatile u32 *)(x)))
@@ -562,6 +611,8 @@ struct mx31_weim {
 #define ESDCTL_BL(x)			((x) << 7)
 #define ESDCTL_PRCT(x)			((x) << 0)
 
+#define ESDCTL_BASE_ADDR	0xB8001000
+
 /* 13 fields of the upper CS control register */
 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
 		cnc, wsc, ew, wws, edc) \
@@ -642,12 +693,23 @@ struct mx31_weim {
 
 /* Register offsets based on IOMUXC_BASE */
 /* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO		0x0c
+#define MUX_CTL_CSPI3_SCLK		0x0d
+#define MUX_CTL_CSPI3_SPI_RDY	0x0e
+#define MUX_CTL_CSPI3_MOSI		0x13
+
 #define MUX_CTL_USBH2_DATA1	0x40
 #define MUX_CTL_USBH2_DIR	0x44
 #define MUX_CTL_USBH2_STP	0x45
 #define MUX_CTL_USBH2_NXT	0x46
 #define MUX_CTL_USBH2_DATA0	0x47
 #define MUX_CTL_USBH2_CLK	0x4B
+
+#define MUX_CTL_TXD2		0x70
+#define MUX_CTL_RTS2		0x71
+#define MUX_CTL_CTS2		0x72
+#define MUX_CTL_RXD2		0x77
+
 #define MUX_CTL_RTS1		0x7c
 #define MUX_CTL_CTS1		0x7d
 #define MUX_CTL_DTR_DCE1	0x7e
@@ -705,6 +767,11 @@ struct mx31_weim {
 #define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
 #define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
 
+#define MUX_RXD2__UART2_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B	IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B	IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)

arch/arm/include/asm/arch-mx35/imx-regs.h

@@ -147,6 +147,19 @@
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define _PLL_BRM(x)	((x) << 31)
+#define _PLL_PD(x)	(((x) - 1) << 26)
+#define _PLL_MFD(x)	(((x) - 1) << 16)
+#define _PLL_MFI(x)	((x) << 10)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
 #define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
 #define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
 #define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
@@ -284,6 +297,23 @@ struct wdog_regs {
 	u16 wmcr;	/* Misc Control */
 };
 
+struct esdc_regs {
+	u32	esdctl0;
+	u32	esdcfg0;
+	u32	esdctl1;
+	u32	esdcfg1;
+	u32	esdmisc;
+	u32	reserved[4];
+	u32	esdcdly[5];
+	u32	esdcdlyl;
+};
+
+#define ESDC_MISC_RST		(1 << 1)
+#define ESDC_MISC_MDDR_EN	(1 << 2)
+#define ESDC_MISC_MDDR_DL_RST	(1 << 3)
+#define ESDC_MISC_DDR_EN	(1 << 8)
+#define ESDC_MISC_DDR2_EN	(1 << 9)
+
 /*
  * NFMS bit in RCSR register for pagesize of nandflash
  */
@@ -293,9 +323,5 @@ struct wdog_regs {
 
 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
 
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern int sdhc_init(void);
-
 #endif
 #endif /* __ASM_ARCH_MX35_H */

arch/arm/include/asm/arch-mx35/lowlevel_macro.S

@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_MPR_CONFIG
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_OPACR_CONFIG
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =MAX_BASE_ADDR
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =MAX_MPR_CONFIG
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =MAX_SGPCR_CONFIG
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =MAX_MGPCR_CONFIG
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =M3IF_BASE_ADDR
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =M3IF_CONFIG
+	str r0, [r1]  /* M3IF control reg */
+.endm
+
+.macro core_init
+	mrc 15, 0, r1, c1, c0, 0
+
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #7
+	mcr 15, 0, r0, c1, c0, 1
+	orr r1, r1, #(1<<11)
+
+	/* Set unaligned access enable */
+	orr r1, r1, #(1<<22)
+
+	/* Set low int latency enable */
+	orr r1, r1, #(1<<21)
+
+	mcr 15, 0, r1, c1, c0, 0
+
+	mov r0, #0
+
+	/* Set branch prediction enable */
+	mcr 15, 0, r0, c15, c2, 4
+
+	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+
+	/*
+	 * initializes very early AIPS
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF
+	 * Also setup the Peripheral Port Remap register inside the core
+	 */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+.endm

arch/arm/include/asm/arch-mx35/mx35_pins.h

@@ -349,6 +349,9 @@ typedef enum iomux_pins {
 	MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
 	MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
 	MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
+
+	MX35_PIN_RTS2_UART3_RXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a0, 0x5e4),
+	MX35_PIN_CTS2_UART3_TXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a4, 0x5e8),
 } iomux_pin_name_t;
 
 #endif

arch/arm/include/asm/arch-omap3/mem.h

@@ -54,79 +54,89 @@ enum {
 #define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
 				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
 
-/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- *   ACTIMA
- *	TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- *	TDPL (Twr) = 15/6	= 2.5 -> 3
- *	TRRD = 12/6	= 2
- *	TRCD = 18/6	= 3
- *	TRP = 18/6	= 3
- *	TRAS = 42/6	= 7
- *	TRC = 60/6	= 10
- *	TRFC = 72/6	= 12
- *   ACTIMB
- *	TCKE = 2
- *	XSR = 120/6 = 20
- */
-#define INFINEON_TDAL_165	6
-#define INFINEON_TDPL_165	3
-#define INFINEON_TRRD_165	2
-#define INFINEON_TRCD_165	3
-#define INFINEON_TRP_165	3
-#define INFINEON_TRAS_165	7
-#define INFINEON_TRC_165	10
-#define INFINEON_TRFC_165	12
-#define INFINEON_V_ACTIMA_165	((INFINEON_TRFC_165 << 27) |		\
-		(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) |	\
-		(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |	\
-		(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) |	\
-		(INFINEON_TDAL_165))
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
+#define ACTIM_CTRLA_TRFC(v)	(((v) & 0x1F) << 27)	/* 31:27 */
+#define ACTIM_CTRLA_TRC(v)	(((v) & 0x1F) << 22)	/* 26:22 */
+#define ACTIM_CTRLA_TRAS(v)	(((v) & 0x0F) << 18)	/* 21:18 */
+#define ACTIM_CTRLA_TRP(v)	(((v) & 0x07) << 15)	/* 17:15 */
+#define ACTIM_CTRLA_TRCD(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLA_TRRD(v)	(((v) & 0x07) << 9)	/* 11:9  */
+#define ACTIM_CTRLA_TDPL(v)	(((v) & 0x07) << 6)	/*  8:6  */
+#define ACTIM_CTRLA_TDAL(v)	(v & 0x1F)		/*  4:0  */
+
+#define ACTIM_CTRLA(a,b,c,d,e,f,g,h)		\
+		ACTIM_CTRLA_TRFC(a)	|	\
+		ACTIM_CTRLA_TRC(b)	|	\
+		ACTIM_CTRLA_TRAS(b)	|	\
+		ACTIM_CTRLA_TRP(d)	|	\
+		ACTIM_CTRLA_TRCD(e)	|	\
+		ACTIM_CTRLA_TRRD(f)	|	\
+		ACTIM_CTRLA_TDPL(g)	|	\
+		ACTIM_CTRLA_TDAL(h)
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
+#define ACTIM_CTRLB_TWTR(v)	(((v) & 0x03) << 16)	/* 17:16 */
+#define ACTIM_CTRLB_TCKE(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLB_TXP(v)	(((v) & 0x07) << 8)	/* 10:8  */
+#define ACTIM_CTRLB_TXSR(v)	(v & 0xFF)		/*  7:0  */
+
+#define ACTIM_CTRLB(a,b,c,d)			\
+		ACTIM_CTRLB_TWTR(a)	|	\
+		ACTIM_CTRLB_TCKE(b)	|	\
+		ACTIM_CTRLB_TXP(b)	|	\
+		ACTIM_CTRLB_TXSR(d)
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
+#define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define INFINEON_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define INFINEON_TRRD_165	2	/* 12/6 = 2			*/
+#define INFINEON_TRCD_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRP_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRAS_165	7	/* 42/6 = 7			*/
+#define INFINEON_TRC_165	10	/* 60/6 = 10			*/
+#define INFINEON_TRFC_165	12	/* 72/6 = 12			*/
+
+#define INFINEON_V_ACTIMA_165	\
+		ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165,	\
+				INFINEON_TRAS_165, INFINEON_TRP_165,	\
+				INFINEON_TRCD_165, INFINEON_TRRD_165,	\
+				INFINEON_TDPL_165, INFINEON_TDAL_165)
 
 #define INFINEON_TWTR_165	1
 #define INFINEON_TCKE_165	2
 #define INFINEON_TXP_165	2
-#define INFINEON_XSR_165	20
-#define INFINEON_V_ACTIMB_165	((INFINEON_TCKE_165 << 12) |		\
-		(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) |	\
-		(INFINEON_TWTR_165 << 16))
-
-/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
- * ACTIMA
- *	TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
- *	TDPL (Twr)	= 15/6	= 2.5 -> 3
- *	TRRD		= 12/6	= 2
- *	TRCD		= 18/6	= 3
- *	TRP		= 18/6	= 3
- *	TRAS		= 42/6	= 7
- *	TRC		= 60/6	= 10
- *	TRFC		= 125/6	= 21
- * ACTIMB
- *	TWTR		= 1
- *	TCKE		= 1
- *	TXSR		= 138/6	= 23
- *	TXP		= 25/6	= 4.1 ~5
- */
-#define MICRON_TDAL_165		6
-#define MICRON_TDPL_165		3
-#define MICRON_TRRD_165		2
-#define MICRON_TRCD_165		3
-#define MICRON_TRP_165		3
-#define MICRON_TRAS_165		7
-#define MICRON_TRC_165		10
-#define MICRON_TRFC_165		21
-#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) |			\
-		(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) |	\
-		(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |	\
-		(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) |	\
-		(MICRON_TDAL_165))
+#define INFINEON_XSR_165	20	/* 120/6 = 20	*/
+
+#define INFINEON_V_ACTIMB_165	\
+		ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165,	\
+				INFINEON_TXP_165, INFINEON_XSR_165)
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
+#define MICRON_TDAL_165		6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define MICRON_TDPL_165		3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define MICRON_TRRD_165		2	/* 12/6 = 2			*/
+#define MICRON_TRCD_165		3	/* 18/6 = 3			*/
+#define MICRON_TRP_165		3	/* 18/6 = 3			*/
+#define MICRON_TRAS_165		7	/* 42/6 = 7			*/
+#define MICRON_TRC_165		10	/* 60/6 = 10			*/
+#define MICRON_TRFC_165		21	/* 125/6 = 21			*/
+
+#define MICRON_V_ACTIMA_165	\
+		ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165,		\
+				MICRON_TRAS_165, MICRON_TRP_165,	\
+				MICRON_TRCD_165, MICRON_TRRD_165,	\
+				MICRON_TDPL_165, MICRON_TDAL_165)
 
 #define MICRON_TWTR_165		1
 #define MICRON_TCKE_165		1
-#define MICRON_XSR_165		23
-#define MICRON_TXP_165		5
-#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) |			\
-		(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) |	\
-		(MICRON_TWTR_165 << 16))
+#define MICRON_XSR_165		23	/* 138/6 = 23		*/
+#define MICRON_TXP_165		5	/* 25/6 = 4.1 => ~5	*/
+
+#define MICRON_V_ACTIMB_165	\
+		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
+				MICRON_TXP_165,	MICRON_XSR_165)
 
 #define MICRON_RAMTYPE			0x1
 #define MICRON_DDRTYPE			0x0
@@ -155,61 +165,48 @@ enum {
 #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
 	(MICRON_SIL << 3) | (MICRON_BL))
 
-/*
- * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
- *   ACTIMA
- *      TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- *      TDPL (Twr) = 15/6 = 2.5 -> 3
- *      TRRD = 12/6 = 2
- *      TRCD = 22.5/6 = 3.75 -> 4
- *      TRP  = 18/6 = 3
- *      TRAS = 42/6 = 7
- *      TRC  = 60/6 = 10
- *      TRFC = 140/6 = 23.3 -> 24
- *   ACTIMB
- *	TWTR = 2
- *	TCKE = 2
- *	TXSR = 200/6 =  33.3 -> 34
- *	TXP  = 1.0 + 1.1 = 2.1 -> 3
- */
-#define NUMONYX_TDAL_165   6
-#define NUMONYX_TDPL_165   3
-#define NUMONYX_TRRD_165   2
-#define NUMONYX_TRCD_165   4
-#define NUMONYX_TRP_165    3
-#define NUMONYX_TRAS_165   7
-#define NUMONYX_TRC_165   10
-#define NUMONYX_TRFC_165  24
-#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
-		(NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
-		(NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
-		(NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
-		(NUMONYX_TDAL_165))
-
-#define NUMONYX_TWTR_165   2
-#define NUMONYX_TCKE_165   2
-#define NUMONYX_TXP_165    3
-#define NUMONYX_XSR_165    34
-#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
-		(NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
-		(NUMONYX_TWTR_165 << 16))
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
+#define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define NUMONYX_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define NUMONYX_TRRD_165	2	/* 12/6 = 2			*/
+#define NUMONYX_TRCD_165	4	/* 22.5/6 = 3.75 -> 4		*/
+#define NUMONYX_TRP_165		3	/* 18/6 = 3			*/
+#define NUMONYX_TRAS_165	7	/* 42/6 = 7			*/
+#define NUMONYX_TRC_165		10	/* 60/6 = 10			*/
+#define NUMONYX_TRFC_165	24	/* 140/6 = 23.3 -> 24		*/
+
+#define NUMONYX_V_ACTIMA_165	\
+		ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165,		\
+				NUMONYX_TRAS_165, NUMONYX_TRP_165,	\
+				NUMONYX_TRCD_165, NUMONYX_TRRD_165,	\
+				NUMONYX_TDPL_165, NUMONYX_TDAL_165)
+
+#define NUMONYX_TWTR_165	2
+#define NUMONYX_TCKE_165	2
+#define NUMONYX_TXP_165		3	/* 200/6 =  33.3 -> 34	*/
+#define NUMONYX_XSR_165		34	/* 1.0 + 1.1 = 2.1 -> 3	*/
+
+#define NUMONYX_V_ACTIMB_165	\
+		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
+				NUMONYX_TXP_165, NUMONYX_XSR_165)
 
 #ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#define V_ACTIMA_165		INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165		INFINEON_V_ACTIMB_165
 #endif
 
 #ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#define V_ACTIMA_165		MICRON_V_ACTIMA_165
+#define V_ACTIMB_165		MICRON_V_ACTIMB_165
 #define V_MCFG			MICRON_V_MCFG
 #define V_RFR_CTRL		MICRON_V_RFR_CTRL
 #define V_MR			MICRON_V_MR
 #endif
 
 #ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#define V_ACTIMA_165		NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165		NUMONYX_V_ACTIMB_165
 #endif
 
 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)

arch/arm/include/asm/arch-pantheon/config.h

@@ -28,6 +28,8 @@
 #include <asm/arch/pantheon.h>
 
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */

board/CarMediaLab/flea3/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= flea3.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/CarMediaLab/flea3/flea3.c

@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG		0x003F4208
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+#define ESDCTL_0x92220000	0x92220000
+#define ESDCTL_0xA2220000	0xA2220000
+#define ESDCTL_0xB2220000	0xB2220000
+#define ESDCTL_0x82228080	0x82228080
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_PRECHARGE	0x00000400
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5	0x00F49F00
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void board_setup_sdram_bank(u32 start_address)
+
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+	u32 *cfg_reg, *ctl_reg;
+	u32 val;
+
+	switch (start_address) {
+	case CSD0_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg0;
+		ctl_reg = &esdc->esdctl0;
+		break;
+	case CSD1_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg1;
+		ctl_reg = &esdc->esdctl1;
+		break;
+	default:
+		return;
+	}
+
+	/* Initialize MISC register for DDR2 */
+	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+	writel(val, &esdc->esdmisc);
+	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+	writel(val, &esdc->esdmisc);
+
+	/*
+	 * according to DDR2 specs, wait a while before
+	 * the PRECHARGE_ALL command
+	 */
+	dram_wait(0x20000);
+
+	/* Load DDR2 config and timing */
+	writel(ESDCTL_DDR2_CONFIG, cfg_reg);
+
+	/* Precharge ALL */
+	writel(ESDCTL_0x92220000,
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Load mode */
+	writel(ESDCTL_0xB2220000,
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+	/* Precharge ALL */
+	writel(ESDCTL_0x92220000,
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Set mode auto refresh : at least two refresh are required */
+	writel(ESDCTL_0xA2220000,
+		ctl_reg);
+	writel(0xda, start_address);
+	writel(0xda, start_address);
+
+	writel(ESDCTL_0xB2220000,
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_MR);
+	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+	/* OCD mode exit */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+	/* Set normal mode */
+	writel(ESDCTL_0x82228080,
+		ctl_reg);
+
+	dram_wait(0x20000);
+
+	/* Do not set delay lines, only for MDDR */
+}
+
+static void board_setup_sdram(void)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/* Initialize with default values both CSD0/1 */
+	writel(0x2000, &esdc->esdctl0);
+	writel(0x2000, &esdc->esdctl1);
+
+	board_setup_sdram_bank(CSD1_BASE_ADDR);
+}
+
+static void setup_iomux_uart3(void)
+{
+	mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+	mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+	int pad;
+
+	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+	mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+	mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+	mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+	mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+	mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+	/* setup pins for FEC */
+	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GPIO3_1 to set HighVCore signal */
+	mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5);
+	gpio_direction_output(65, 1);
+
+	/* initialize PLL and clock configuration */
+	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+	writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+	/* Set the core to run at 532 Mhz */
+	writel(0x00001000, &ccm->pdr0);
+
+	/* Set-up RAM */
+	board_setup_sdram();
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDI0_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_I2C3_MASK,
+		&ccm->cgr1);
+
+	/* Set-up NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	/* Set pinmux for the required peripherals */
+	setup_iomux_uart3();
+	setup_iomux_i2c();
+	setup_iomux_fec();
+	setup_iomux_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}

board/CarMediaLab/flea3/lowlevel_init.S

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_OPACR_CONFIG	0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG		0x00000040
+
+#define CCM_PDR0_CONFIG		0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	core_init
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	mov pc, lr

board/LaCie/netspace_v2/kwbimage-is2.cfg

@@ -0,0 +1,162 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000008	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0

board/LaCie/netspace_v2/kwbimage.cfg

@@ -69,8 +69,8 @@ DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
 # bit12-11: TW2W
 # bit31-13: zero required
 
-DATA 0xFFD01410 0x0000CCCC	#  DDR Address Control
-# bit1-0:   01, Cs0width=x16
+DATA 0xFFD01410 0x0000000C	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
 # bit3-2:   11, Cs0size=1Gb
 # bit5-4:   00, Cs2width=nonexistent
 # bit7-6:   00, Cs1size =nonexistent

board/LaCie/netspace_v2/netspace_v2.c

@@ -24,6 +24,7 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <command.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/gpio.h>

board/Marvell/dreamplug/dreamplug.c

@@ -27,6 +27,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "dreamplug.h"

board/Seagate/dockstar/dockstar.c

@@ -29,6 +29,8 @@
 #include <miiphy.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
 #include "dockstar.h"
 
 DECLARE_GLOBAL_DATA_PTR;

board/ait/cam_enc_4xx/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/ait/cam_enc_4xx/cam_enc_4xx.c

@@ -0,0 +1,446 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+static struct davinci_timer *timer =
+	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+static unsigned long get_timer_val(void)
+{
+	unsigned long now = readl(&timer->tim34);
+
+	return now;
+}
+
+static void stop_timer(void)
+{
+	writel(0x0, &timer->tcr);
+	return;
+}
+
+int checkboard(void)
+{
+	printf("Board: AIT CAM ENC 4XX\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+	davinci_emac_initialize();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+				   uint8_t *buf, int page)
+{
+	struct nand_chip *this = mtd->priv;
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+	chip->read_buf(mtd, oob, mtd->oobsize);
+
+	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		int stat;
+
+		chip->ecc.hwctl(mtd, NAND_ECC_READ);
+		chip->read_buf(mtd, p, eccsize);
+		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+		if (chip->ecc.prepad)
+			oob += chip->ecc.prepad;
+
+		stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+		if (stat == -1)
+			mtd->ecc_stats.failed++;
+		else
+			mtd->ecc_stats.corrected += stat;
+
+		oob += eccbytes;
+
+		if (chip->ecc.postpad)
+			oob += chip->ecc.postpad;
+	}
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->read_buf(mtd, oob, i);
+
+	return 0;
+}
+
+static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
+				    struct nand_chip *chip, const uint8_t *buf)
+{
+	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+	struct nand_chip *this = mtd->priv;
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+	int offset = 0;
+	const uint8_t *p = buf;
+	uint8_t *oob = chip->oob_poi;
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+		chip->write_buf(mtd, p, eccsize);
+
+		/* Calculate ECC without prepad */
+		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+		if (chip->ecc.prepad) {
+			offset = (chip->ecc.steps - eccsteps) * chunk;
+			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+			oob += chip->ecc.prepad;
+		}
+
+		offset = ((chip->ecc.steps - eccsteps) * chunk) +
+				chip->ecc.prepad;
+		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+		oob += eccbytes;
+
+		if (chip->ecc.postpad) {
+			offset = ((chip->ecc.steps - eccsteps) * chunk) +
+					chip->ecc.prepad + eccbytes;
+			memcpy(&davinci_ecc_buf[offset], oob,
+				chip->ecc.postpad);
+			oob += chip->ecc.postpad;
+		}
+	}
+
+	/*
+	 * Write the sparebytes into the page once
+	 * all eccsteps have been covered
+	 */
+	for (i = 0; i < mtd->oobsize; i++)
+		writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
+
+	/* Calculate remaining oob bytes */
+	i = mtd->oobsize - (oob - chip->oob_poi);
+	if (i)
+		chip->write_buf(mtd, oob, i);
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+				   struct nand_chip *chip, int page)
+{
+	int pos, status = 0;
+	const uint8_t *bufpoi = chip->oob_poi;
+
+	pos = mtd->writesize;
+
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+	chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
+	struct nand_chip *chip, int page, int sndcmd)
+{
+	struct nand_chip *this = mtd->priv;
+	uint8_t *buf = chip->oob_poi;
+	uint8_t *bufpoi = buf;
+
+	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+	chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+	return 1;
+}
+
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip	*this = mtd->priv;
+	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
+	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
+
+	if (chip == 1) {
+		__set_bit(14, &wbase);
+		__set_bit(14, &rbase);
+	} else {
+		__clear_bit(14, &wbase);
+		__clear_bit(14, &rbase);
+	}
+	this->IO_ADDR_W = (void *)wbase;
+	this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_dm365evm_select_chip;
+
+	return 0;
+}
+
+struct nand_ecc_ctrl org_ecc;
+static int notsaved = 1;
+
+static int nand_switch_hw_func(int mode)
+{
+	struct nand_chip *nand;
+	struct mtd_info *mtd;
+
+	if (nand_curr_device < 0 ||
+	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+	    !nand_info[nand_curr_device].name) {
+		printf("Error: Can't switch hw functions," \
+			" no devices available\n");
+		return -1;
+	}
+
+	mtd = &nand_info[nand_curr_device];
+	nand = mtd->priv;
+
+	if (mode == 0) {
+		printf("switching to uboot hw functions.\n");
+		memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
+	} else {
+		/* RBL */
+		printf("switching to RBL hw functions.\n");
+		if (notsaved == 1) {
+			memcpy(&org_ecc, &nand->ecc,
+				sizeof(struct nand_ecc_ctrl));
+			notsaved = 0;
+		}
+		nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+		nand->ecc.prepad = 6;
+		nand->ecc.read_page = davinci_std_read_page_syndrome;
+		nand->ecc.write_page = davinci_std_write_page_syndrome;
+		nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+		nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+	}
+	return mode;
+}
+
+static int hwmode;
+
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+		char *const argv[])
+{
+	if (argc != 2)
+		goto usage;
+	if (strncmp(argv[1], "rbl", 2) == 0)
+		hwmode = nand_switch_hw_func(1);
+	else if (strncmp(argv[1], "uboot", 2) == 0)
+		hwmode = nand_switch_hw_func(0);
+	else
+		goto usage;
+
+	return 0;
+
+usage:
+	printf("Usage: nandrbl %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandrbl, 2, 1,	do_switch_ecc,
+	"switch between rbl/uboot NAND ECC calculation algorithm",
+	"[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
+);
+
+
+#endif /* #ifdef CONFIG_NAND_DAVINCI */
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+	.input_clk	= 121500000,
+	.host_caps	= MMC_MODE_4BIT,
+	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
+	.version	= MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int err;
+
+	/* Add slot-0 to mmc subsystem */
+	err = davinci_mmc_init(bis, &mmc_sd0);
+
+	return err;
+}
+#endif
+
+int board_late_init(void)
+{
+	struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+	/* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
+	while (get_timer_val() < 0x186a00)
+		;
+
+	/* 1 sec reached -> stop timer, clear all LED */
+	stop_timer();
+	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+	return 0;
+}
+
+void reset_phy(void)
+{
+	char *name = "GENERIC @ 0x00";
+
+	/* reset the phy */
+	miiphy_reset(name, 0x0);
+}
+
+#else /* #ifndef CONFIG_SPL_BUILD */
+static void cam_enc_4xx_set_all_led(void)
+{
+	struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+	setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+}
+
+/*
+ * TIMER 0 is used for tick
+ */
+static struct davinci_timer *timer =
+	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIM_CLK_DIV	16
+
+static int cam_enc_4xx_timer_init(void)
+{
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	writel(0x0, &timer->tcr);
+	writel(0x0, &timer->tgcr);
+	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+	writel(0x0, &timer->tim34);
+	writel(TIMER_LOAD_VAL, &timer->prd34);
+	writel(2 << 22, &timer->tcr);
+	return 0;
+}
+
+void board_gpio_init(void)
+{
+	struct davinci_gpio *gpio;
+
+	cam_enc_4xx_set_all_led();
+	cam_enc_4xx_timer_init();
+	gpio = davinci_gpio_bank01;
+	clrbits_le32(&gpio->dir, ~0xfdfffffe);
+	/* clear LED D14 = GPIO25 */
+	clrbits_le32(&gpio->out_data, 0x02000000);
+	gpio = davinci_gpio_bank23;
+	clrbits_le32(&gpio->dir, ~0x5ff0afef);
+	/* set GPIO61 to 1 -> intern UART0 as Console */
+	setbits_le32(&gpio->out_data, 0x20000000);
+	/*
+	 * PHY out of reset GIO 50 = 1
+	 * NAND WP off GIO 51 = 1
+	 */
+	setbits_le32(&gpio->out_data, 0x000c0004);
+	gpio = davinci_gpio_bank45;
+	clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
+	/*
+	 * clear LED:
+	 * D17 = GPIO86
+	 * D11 = GPIO87
+	 * GPIO88
+	 * GPIO89
+	 * D13 = GPIO90
+	 * GPIO91
+	 */
+	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+	gpio = davinci_gpio_bank67;
+	clrbits_le32(&gpio->dir, ~0x000007ff);
+}
+
+/*
+ * functions for the post memory test.
+ */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	*vstart = CONFIG_SYS_SDRAM_BASE;
+	*size = PHYS_SDRAM_1_SIZE;
+	*phys_offset = 0;
+	return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+	cam_enc_4xx_set_all_led();
+	puts("mem failure\n");
+	while (1)
+		;
+}
+#endif

board/ait/cam_enc_4xx/config.mk

@@ -0,0 +1,15 @@
+#
+# 	AIT cam_enc_4xx board
+#	cam_enc_4xx board has 1 bank of 256 MB DDR RAM
+#	Physical Address: 8000'0000 to 9000'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+PAD_TO	:= 12320
+UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
+ifndef CONFIG_SPL_BUILD
+ALL-y += $(obj)u-boot.ubl
+endif

mmc_spl/board/samsung/smdkv310/u-boot.lds → board/ait/cam_enc_4xx/u-boot-spl.lds

@@ -1,13 +1,10 @@
 /*
- * (C) Copyright 2011
- * Chander Kashyap, Samsung Electronics, <k.chander@samsung.com>
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
  * (C) Copyright 2002
  * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -18,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,6 +24,9 @@
  * MA 02111-1307 USA
  */
 
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
@@ -35,54 +35,39 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text	:
+	.text      :
 	{
-		start.o	(.text)
-		*(.text)
-	}
+	__start = .;
+	  arch/arm/cpu/arm926ejs/start.o	(.text)
+	  *(.text*)
+	} >.sram
 
 	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
 
 	. = ALIGN(4);
-	.data : {
-		*(.data)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 	. = ALIGN(4);
-
-	__image_copy_end = .;
-
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
 		__rel_dyn_end = .;
-	}
+	} >.sram
 
 	.dynsym : {
 		__dynsym_start = .;
 		*(.dynsym)
-	}
-
-	_end = .;
+	} >.sram
 
-	.bss __rel_dyn_start (OVERLAY) : {
+	.bss :
+	{
+		. = ALIGN(4);
 		__bss_start = .;
-		*(.bss)
-		 . = ALIGN(4);
+		*(.bss*)
+		. = ALIGN(4);
 		__bss_end__ = .;
-	}
+	} >.sram
 
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	__image_copy_end = .;
+	_end = .;
 }

board/ait/cam_enc_4xx/ublimage.cfg

@@ -0,0 +1,48 @@
+#
+# (C Copyright 2011
+# Heiko Schocher DENX Software Engineering hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer doc/README.ublimage for more details about how-to configure
+# and create ublimage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# UBL special mode : one of
+# safe (the board has no nand neither onenand)
+MODE	safe
+
+# Entry point address for the user bootloader (absolute address)
+# nand spl TEXT_BASE = 0x20 !!
+ENTRY	0x00000020
+
+# Number of pages (size of user bootloader in number of pages)
+# @ nand spl 6 pages
+PAGES	6
+
+# Block number where user bootloader is present
+# RBL starts always with block 1
+START_BLOCK	5
+
+# Page number where user bootloader is present
+# Page 0 is always UBL header
+START_PAGE	0
+
+LD_ADDR		0x20

board/comelit/dig297/dig297.c

@@ -91,8 +91,6 @@ static const u32 gpmc_lan_config[] = {
 int board_init(void)
 {
 	gpmc_init();		/* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 

board/davedenx/qong/qong.c

@@ -120,12 +120,6 @@ int board_early_init_f(void)
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 
 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -143,7 +137,7 @@ int board_early_init_f(void)
 	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
 	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
 
-	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+	mx31_set_gpr(MUX_PGP_UH2, 1);
 
 	return 0;
 

board/davinci/common/misc.c

@@ -33,7 +33,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */

board/davinci/ea20/ea20.c

@@ -35,11 +35,28 @@
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/da8xx-fb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
 
+static const struct da8xx_panel lcd_panel = {
+	/* Casio COM57H531x */
+	.name = "Casio_COM57H531x",
+	.width = 640,
+	.height = 480,
+	.hfp = 12,
+	.hbp = 144,
+	.hsw = 30,
+	.vfp = 10,
+	.vbp = 35,
+	.vsw = 3,
+	.pxl_clk = 25000000,
+	.invert_pxl_clk = 0,
+};
+
 /* SPI0 pin muxer settings */
 static const struct pinmux_config spi1_pins[] = {
 	{ pinmux(5), 1, 1 },
@@ -48,12 +65,18 @@ static const struct pinmux_config spi1_pins[] = {
 	{ pinmux(5), 1, 5 }
 };
 
-/* UART pin muxer settings */
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux(4), 2, 2 },
+	{ pinmux(4), 2, 3 }
+};
+
+/* UART0 pin muxer settings */
 static const struct pinmux_config uart_pins[] = {
-	{ pinmux(0), 4, 6 },
-	{ pinmux(0), 4, 7 },
-	{ pinmux(4), 2, 4 },
-	{ pinmux(4), 2, 5 }
+	{ pinmux(3), 2, 7 },
+	{ pinmux(3), 2, 6 },
+	{ pinmux(3), 2, 4 },
+	{ pinmux(3), 2, 5 }
 };
 
 #ifdef CONFIG_DRIVER_TI_EMAC
@@ -73,70 +96,136 @@ static const struct pinmux_config emac_pins[] = {
 
 #ifdef CONFIG_NAND_DAVINCI
 const struct pinmux_config nand_pins[] = {
-	{ pinmux(7), 1, 1 },
-	{ pinmux(7), 1, 2 },
-	{ pinmux(7), 1, 4 },
-	{ pinmux(7), 1, 5 },
-	{ pinmux(9), 1, 0 },
-	{ pinmux(9), 1, 1 },
-	{ pinmux(9), 1, 2 },
-	{ pinmux(9), 1, 3 },
-	{ pinmux(9), 1, 4 },
-	{ pinmux(9), 1, 5 },
-	{ pinmux(9), 1, 6 },
-	{ pinmux(9), 1, 7 },
-	{ pinmux(12), 1, 5 },
-	{ pinmux(12), 1, 6 }
+	{ pinmux(7), 1, 0},	/* CS2 */
+	{ pinmux(7), 0, 1},	/* CS3  in three state*/
+	{ pinmux(7), 1, 4 },	/* EMA_WE */
+	{ pinmux(7), 1, 5 },	/* EMA_OE */
+	{ pinmux(9), 1, 0 },	/* EMA_D[7] */
+	{ pinmux(9), 1, 1 },	/* EMA_D[6] */
+	{ pinmux(9), 1, 2 },	/* EMA_D[5] */
+	{ pinmux(9), 1, 3 },	/* EMA_D[4] */
+	{ pinmux(9), 1, 4 },	/* EMA_D[3] */
+	{ pinmux(9), 1, 5 },	/* EMA_D[2] */
+	{ pinmux(9), 1, 6 },	/* EMA_D[1] */
+	{ pinmux(9), 1, 7 },	/* EMA_D[0] */
+	{ pinmux(12), 1, 5 },	/* EMA_A[2] */
+	{ pinmux(12), 1, 6 },	/* EMA_A[1] */
+	{ pinmux(6), 1, 0 }	/* EMA_CLK */
 };
 #endif
 
+const struct pinmux_config gpio_pins[] = {
+	{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
+	{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
+	{ pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+	{ pinmux(19), 8, 5 }, /* GPIO6[1]  DISP_ON */
+	{ pinmux(14), 8, 1 }  /* GPIO6[6]  LCD_B_PWR*/
+};
+
+const struct pinmux_config lcd_pins[] = {
+	{ pinmux(17), 2, 1 }, /* LCD_D_0 */
+	{ pinmux(17), 2, 0 }, /* LCD_D_1 */
+	{ pinmux(16), 2, 7 }, /* LCD_D_2 */
+	{ pinmux(16), 2, 6 }, /* LCD_D_3 */
+	{ pinmux(16), 2, 5 }, /* LCD_D_4 */
+	{ pinmux(16), 2, 4 }, /* LCD_D_5 */
+	{ pinmux(16), 2, 3 }, /* LCD_D_6 */
+	{ pinmux(16), 2, 2 }, /* LCD_D_7 */
+	{ pinmux(18), 2, 1 }, /* LCD_D_8 */
+	{ pinmux(18), 2, 0 }, /* LCD_D_9 */
+	{ pinmux(17), 2, 7 }, /* LCD_D_10 */
+	{ pinmux(17), 2, 6 }, /* LCD_D_11 */
+	{ pinmux(17), 2, 5 }, /* LCD_D_12 */
+	{ pinmux(17), 2, 4 }, /* LCD_D_13 */
+	{ pinmux(17), 2, 3 }, /* LCD_D_14 */
+	{ pinmux(17), 2, 2 }, /* LCD_D_15 */
+	{ pinmux(18), 2, 6 }, /* LCD_PCLK */
+	{ pinmux(19), 2, 0 }, /* LCD_HSYNC */
+	{ pinmux(19), 2, 1 }, /* LCD_VSYNC */
+	{ pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
+};
+
+const struct pinmux_config halten_pin[] = {
+	{ pinmux(3),  4, 2 } /* GPIO8[6] HALTEN */
+};
+
 static const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_SPI_FLASH
 	PINMUX_ITEM(spi1_pins),
 #endif
 	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
 #ifdef CONFIG_NAND_DAVINCI
 	PINMUX_ITEM(nand_pins),
 #endif
+#ifdef CONFIG_VIDEO
+	PINMUX_ITEM(lcd_pins),
+#endif
 };
 
 static const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
 	{ DAVINCI_LPSC_EMAC },	/* image download */
-	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_UART0 },	/* console */
 	{ DAVINCI_LPSC_GPIO },
+	{ DAVINCI_LPSC_LCDC }, /* LCD */
 };
 
-int board_init(void)
+int board_early_init_f(void)
 {
+	struct davinci_gpio *gpio6_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+	/* PinMux for GPIO */
+	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+		return 1;
+
+	/* Set the RESETOUTn low */
+	writel((readl(&gpio6_base->set_data) & ~(1 << 15)),
+		&gpio6_base->set_data);
+	writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir);
+
+	/* Set U0_SW0 low for UART0 as console*/
+	writel((readl(&gpio6_base->set_data) & ~(1 << 10)),
+		&gpio6_base->set_data);
+	writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir);
+
+	/* Set U0_SW1 low for UART0 as console*/
+	writel((readl(&gpio6_base->set_data) & ~(1 << 12)),
+		&gpio6_base->set_data);
+	writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir);
+
+	/* Set LCD_B_PWR low to power down LCD Backlight*/
+	writel((readl(&gpio6_base->set_data) & ~(1 << 6)),
+		&gpio6_base->set_data);
+	writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir);
+
+	/* Set DISP_ON low to disable LCD output*/
+	writel((readl(&gpio6_base->set_data) & ~(1 << 1)),
+		&gpio6_base->set_data);
+	writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir);
+
 #ifndef CONFIG_USE_IRQ
 	irq_init();
 #endif
 
-
-#ifdef CONFIG_NAND_DAVINCI
 	/*
 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
 	 * Linux kernel @ 25MHz EMIFA
 	 */
+#ifdef CONFIG_NAND_DAVINCI
 	writel((DAVINCI_ABCR_WSETUP(0) |
-		DAVINCI_ABCR_WSTROBE(0) |
+		DAVINCI_ABCR_WSTROBE(1) |
 		DAVINCI_ABCR_WHOLD(0) |
 		DAVINCI_ABCR_RSETUP(0) |
 		DAVINCI_ABCR_RSTROBE(1) |
 		DAVINCI_ABCR_RHOLD(0) |
 		DAVINCI_ABCR_TA(0) |
 		DAVINCI_ABCR_ASIZE_8BIT),
-	       &davinci_emif_regs->ab2cr); /* CS3 */
+	       &davinci_emif_regs->ab1cr); /* CS2 */
 #endif
 
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_EA20;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
 	/*
 	 * Power on required peripherals
 	 * ARM does not have access by default to PSC0 and PSC1
@@ -150,7 +239,7 @@ int board_init(void)
 	writel(readl(&davinci_syscfg_regs->suspsrc) &
 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
-		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+		 DAVINCI_SYSCFG_SUSPSRC_UART0),
 	       &davinci_syscfg_regs->suspsrc);
 
 	/* configure pinmux settings */
@@ -167,10 +256,60 @@ int board_init(void)
 	/* enable the console UART */
 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
-	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
+
+	/*
+	 * Reconfigure the LCDC priority to the highest to ensure that
+	 * the throughput/latency requirements for the LCDC are met.
+	 */
+	writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
+	       &davinci_syscfg_regs->mstpri[2]);
+
+	/* Set LCD_B_PWR low to power up LCD Backlight*/
+	writel((readl(&gpio6_base->set_data)  | (1 << 6)),
+		&gpio6_base->set_data);
+
+	/* Set DISP_ON low to disable LCD output*/
+	writel((readl(&gpio6_base->set_data) | (1 << 1)),
+		&gpio6_base->set_data);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	da8xx_video_init(&lcd_panel, 16);
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+
+int board_late_init(void)
+{
+	struct davinci_gpio *gpio8_base =
+			(struct davinci_gpio *)DAVINCI_GPIO_BANK8;
+
+	/* PinMux for HALTEN */
+	if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
+		return 1;
+
+	/* Set HALTEN to high */
+	writel((readl(&gpio8_base->set_data) | (1 << 6)),
+		&gpio8_base->set_data);
+	writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir);
+
+	setenv("stdout", "serial");
 
 	return 0;
 }
+#endif /* BOARD_LATE_INIT */
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 

board/freescale/mx31pdk/mx31pdk.c

@@ -30,6 +30,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <watchdog.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -69,16 +71,34 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	enable_caches();
+
 	return 0;
 }
 
 int board_late_init(void)
 {
+	u32 val;
+	struct pmic *p;
+
+	pmic_init();
+	p = get_pmic();
+
+	/* Enable RTC battery */
+	pmic_reg_read(p, REG_POWER_CTL0, &val);
+	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 #ifdef CONFIG_HW_WATCHDOG
 	mxc_hw_watchdog_enable();
 #endif

board/freescale/mx35pdk/mx35pdk.h

@@ -59,24 +59,6 @@
 #define CCM_CCMR_CONFIG		0x003F4208
 #define CCM_PDR0_CONFIG		0x00801000
 
-#define PLL_BRM_OFFSET	31
-#define PLL_PD_OFFSET	26
-#define PLL_MFD_OFFSET	16
-#define PLL_MFI_OFFSET	10
-
-#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
-#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
-#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
-#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
-#define _PLL_MFN(x)	(x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
-	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
-	 _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
 /* MEMORY SETTING */
 #define ESDCTL_0x92220000	0x92220000
 #define ESDCTL_0xA2220000	0xA2220000

board/freescale/mx51evk/mx51evk.c

@@ -38,8 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static u32 system_rev;
-
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR, 1},
@@ -47,11 +45,6 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
 };
 #endif
 
-u32 get_board_rev(void)
-{
-	return system_rev;
-}
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -254,16 +247,14 @@ static void power_init(void)
 	pmic_reg_write(p, REG_MODE_1, val);
 	udelay(200);
 
-	gpio_direction_output(46, 0);
-
-	/* Reset the ethernet controller over GPIO */
-	writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
 	/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 	val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 		VVIDEOEN | VAUDIOEN  | VSDEN;
 	pmic_reg_write(p, REG_MODE_1, val);
 
+	mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+	gpio_direction_output(46, 0);
+
 	udelay(500);
 
 	gpio_set_value(46, 1);
@@ -406,8 +397,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	system_rev = get_cpu_rev();
-
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 

board/freescale/mx53ard/mx53ard.c

@@ -37,11 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-
 int dram_init(void)
 {
 	u32 size1, size2;

board/freescale/mx53evk/mx53evk.c

@@ -39,11 +39,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */

board/freescale/mx53loco/mx53loco.c

@@ -38,11 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-
 int dram_init(void)
 {
 	u32 size1, size2;

board/freescale/mx53smd/mx53smd.c

@@ -35,11 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 get_board_rev(void)
-{
-	return get_cpu_rev();
-}
-
 int dram_init(void)
 {
 	u32 size1, size2;

board/hale/tt01/Makefile

@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+COBJS	:= tt01.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/hale/tt01/lowlevel_init.S

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr	r0, =ARM_PPMRR      /* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+	mov	pc, lr

board/hale/tt01/tt01.c

@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_STRING	"Board: HALE TT-01"
+
+/* Clock configuration */
+#define CCM_CCMR_SETUP		0x074B0BF5
+
+static void board_setup_clocks(void)
+{
+	struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
+	volatile int wait = 0x10000;
+
+	writel(CCM_CCMR_SETUP, &ccm->ccmr);
+	while (wait--)
+		;
+
+	writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
+	writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
+
+	/* Set up clock to 532MHz */
+	writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+			PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
+			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
+			PDR0_MCU_PODF(0), &ccm->pdr0);
+	writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
+			&ccm->mpctl);
+	writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
+			&ccm->spctl);
+}
+
+/* DRAM configuration */
+
+#define ESDMISC_MDDR_SETUP	0x00000004
+#define ESDMISC_MDDR_RESET_DL	0x0000000c
+/*
+ * decoding magic 0x6ac73a = 0b 0110 1010   1100 0111   0011 1010 below:
+ *   tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
+ *   tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
+ *   tRCD = 011, tRC = 010
+ *  note: all but tWTR (1), tRC (111) are reset defaults,
+ *     the same values work in the jtag configuration
+ *
+ *  Bluetechnix setup has 0x75e73a (for 128MB) =
+ *			0b 0111 0101   1110 0111   0011 1010
+ *   tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
+ *   tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
+ *   tRCD = 011, tRC = 010
+ */
+#define ESDCFG0_MDDR_SETUP	0x006ac73a
+#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW		ESDCTL_SETTINGS
+
+static void board_setup_sdram(void)
+{
+	u32 *pad;
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/*
+	 * setup pad control for the controller pins
+	 * no loopback, no pull, no keeper, no open drain,
+	 * standard input, standard drive, slow slew rate
+	 */
+	for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
+			pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
+		*pad = 0;
+
+	/* set up MX31 DDR Memory Controller */
+	writel(ESDMISC_MDDR_SETUP, &esdc->misc);
+	writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
+
+	/* perform DDR init sequence for CSD0 */
+	writel(ESDCTL_PRECHARGE, &esdc->ctl0);
+	writel(0x12344321, CSD0_BASE+0x0f00);
+	writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
+	writel(0x12344321, CSD0_BASE);
+	writel(0x12344321, CSD0_BASE);
+	writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
+	writeb(0xda, CSD0_BASE+0x33);
+	writeb(0xff, CSD0_BASE+0x1000000);
+	writel(ESDCTL_RW, &esdc->ctl0);
+	writel(0xDEADBEEF, CSD0_BASE);
+	writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
+}
+
+static void tt01_spi3_hw_init(void)
+{
+	/* CSPI3 */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
+	/* CSPI3, SS0 = Atlas */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
+
+	/* start CSPI3 clock (3 = always on except if PLL off) */
+	setbits_le32(CCM_CGR0, 3 << 16);
+}
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+			PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* CS4: FPGA incl. network controller */
+	struct mxc_weimcs cs4 = {
+		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 28, 1,  7,  6),
+		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+		CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
+		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+		CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,  1,   0)
+	};
+
+	/* this seems essential, won't start without, but why? */
+	writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
+
+	board_setup_clocks();
+	board_setup_sdram();
+	mxc_setup_weimcs(4, &cs4);
+
+	/* Setup UART2 and SPI3 pins */
+	mx31_uart2_hw_init();
+	tt01_spi3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	pmic_init();
+
+#ifdef CONFIG_HW_WATCHDOG
+	mxc_hw_watchdog_enable();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts(BOARD_STRING "\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}

board/karo/tx25/tx25.c

@@ -140,7 +140,6 @@ int board_init()
 	mx25_uart1_init_pins();
 #endif
 	/* board id for linux */
-	gd->bd->bi_arch_number = MACH_TYPE_TX25;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 	return 0;
 }

board/keymile/km_arm/km_arm.c

@@ -207,8 +207,14 @@ int misc_init_r(void)
 	if (wait_for_ne != NULL) {
 		if (strcmp(wait_for_ne, "true") == 0) {
 			int cnt = 0;
+			int abort = 0;
 			puts("NE go: ");
 			while (startup_allowed() == 0) {
+				if (tstc()) {
+					(void) getc(); /* consume input */
+					abort = 1;
+					break;
+				}
 				udelay(200000);
 				cnt++;
 				if (cnt == 5)
@@ -218,7 +224,10 @@ int misc_init_r(void)
 					puts("    \b\b\b\b");
 				}
 			}
-			puts("OK\n");
+			if (abort == 1)
+				printf("\nAbort waiting for ne\n");
+			else
+				puts("OK\n");
 		}
 	}
 #endif
@@ -258,17 +267,17 @@ int board_early_init_f(void)
 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 #endif
-
+#if defined(CONFIG_KM_RECONFIG_XLX)
+	/* trigger the reconfiguration of the xilinx fpga */
+	kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+	kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+	kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+#endif
 	return 0;
 }
 
 int board_init(void)
 {
-	/*
-	 * arch number of board
-	 */
-	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
@@ -396,6 +405,15 @@ int hush_init_var(void)
 #endif
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT)
+const ulong patterns[]      = {	0x00000000,
+				0xFFFFFFFF,
+				0xFF00FF00,
+				0x0F0F0F0F,
+				0xF0F0F0F0};
+const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns);
+const ulong OFFS_PATTERN    = 3;
+const ulong REPEAT_PATTERN  = 1000;
+
 void bootcount_store(ulong a)
 {
 	volatile ulong *save_addr;
@@ -407,21 +425,34 @@ void bootcount_store(ulong a)
 	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
 	writel(a, save_addr);
 	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
+
+	for (i = 0; i < REPEAT_PATTERN; i++)
+		writel(patterns[i % NBR_OF_PATTERNS],
+			&save_addr[i+OFFS_PATTERN]);
+
 }
 
 ulong bootcount_load(void)
 {
 	volatile ulong *save_addr;
 	volatile ulong size = 0;
-	int i;
+	ulong counter = 0;
+	int i, tmp;
+
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		size += gd->bd->bi_dram[i].size;
 	}
 	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
-	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
-		return 0;
-	else
-		return readl(save_addr);
+
+	counter = readl(&save_addr[0]);
+
+	/* Is the counter reliable, check in the big pattern for bit errors */
+	for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
+		tmp = readl(&save_addr[i+OFFS_PATTERN]);
+		if (tmp != patterns[i % NBR_OF_PATTERNS])
+			counter = 0;
+	}
+	return counter;
 }
 #endif
 

board/matrix_vision/mvblx/Makefile

@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS	:= $(COBJS-y)
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/matrix_vision/mvblx/config.mk

@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000

board/matrix_vision/mvblx/fpga.c

@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+	fpga_null_fn,   /* Altera_pre_fn */
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_null_fn,
+	fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+	Altera_CYC2,
+	fast_passive_parallel,
+	Altera_EP3C5_SIZE,
+	(void *) &altera_fns,
+	NULL,
+	0
+};
+
+#define GPIO_RESET		43
+#define GPIO_DCLK		65
+#define GPIO_nSTATUS	157
+#define GPIO_CONF_DONE	158
+#define GPIO_nCONFIG	159
+#define GPIO_DATA0		54
+#define GPIO_DATA1		55
+#define GPIO_DATA2		56
+#define GPIO_DATA3		57
+#define GPIO_DATA4		58
+#define GPIO_DATA5		60
+#define GPIO_DATA6		61
+#define GPIO_DATA7		62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+	fpga_debug("Initializing FPGA interface\n");
+	fpga_init();
+	fpga_add(fpga_altera, &cyclone2);
+
+	if (gpio_request(GPIO_DCLK, "dclk") ||
+			gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+			gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+			gpio_request(GPIO_nCONFIG, "nConfig") ||
+			gpio_request(GPIO_DATA0, "data0") ||
+			gpio_request(GPIO_DATA1, "data1") ||
+			gpio_request(GPIO_DATA2, "data2") ||
+			gpio_request(GPIO_DATA3, "data3") ||
+			gpio_request(GPIO_DATA4, "data4") ||
+			gpio_request(GPIO_DATA5, "data5") ||
+			gpio_request(GPIO_DATA6, "data6") ||
+			gpio_request(GPIO_DATA7, "data7")) {
+		printf("%s: error requesting GPIOs.", __func__);
+		return FPGA_FAIL;
+	}
+
+	/* set up outputs */
+	gpio_direction_output(GPIO_DCLK,  0);
+	gpio_direction_output(GPIO_nCONFIG, 0);
+	gpio_direction_output(GPIO_DATA0, 0);
+	gpio_direction_output(GPIO_DATA1, 0);
+	gpio_direction_output(GPIO_DATA2, 0);
+	gpio_direction_output(GPIO_DATA3, 0);
+	gpio_direction_output(GPIO_DATA4, 0);
+	gpio_direction_output(GPIO_DATA5, 0);
+	gpio_direction_output(GPIO_DATA6, 0);
+	gpio_direction_output(GPIO_DATA7, 0);
+
+	/* NB omap_free_gpio() resets to an input, so we can't
+	 * free ie. nCONFIG, or else the FPGA would reset
+	 * Q: presumably gpio_free() has the same effect?
+	 */
+
+	/* set up inputs */
+	gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+	gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+	fpga_config_fn(0, 1, 0);
+	udelay(60);
+
+	return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+	return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+	fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+	if (flush) {
+		gpio_set_value(GPIO_nCONFIG, !assert);
+		udelay(1);
+		gpio_set_value(GPIO_nCONFIG, assert);
+	}
+
+	return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+	int result = 0;
+
+	/* since revA of BLX, we will not get this signal. */
+	udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+	fpga_debug("not waiting for CONF_DONE.");
+	result = 1;
+#else
+	fpga_debug("CONF_DONE check ... ");
+	if (gpio_get_value(GPIO_CONF_DONE))  {
+		fpga_debug("high\n");
+		result = 1;
+	} else
+		fpga_debug("low\n");
+	gpio_free(GPIO_CONF_DONE);
+#endif
+
+	return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+	int result = 0;
+	fpga_debug("STATUS check ... ");
+
+	result = gpio_get_value(GPIO_nSTATUS);
+
+	if (result < 0)
+		fpga_debug("error\n");
+	else if (result > 0)
+		fpga_debug("high\n");
+	else
+		fpga_debug("low\n");
+
+	return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+	gpio_set_value(GPIO_DATA0, byte & 0x01);
+	gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+	gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+	gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+	gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+	gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+	gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+	gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+	/* clock */
+	gpio_set_value(GPIO_DCLK, 1);
+	udelay(1);
+	gpio_set_value(GPIO_DCLK, 0);
+	udelay(1);
+
+	return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+	unsigned char *data = (unsigned char *) buf;
+	int i;
+
+	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+	for (i = 0; i < len; i++)
+		_write_fpga(data[i]);
+	fpga_debug("-%s\n", __func__);
+
+	return FPGA_SUCCESS;
+}

board/matrix_vision/mvblx/fpga.h

@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);

board/matrix_vision/mvblx/mvblx.c

@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init();	/* in SRAM or SDRAM, finish GPMC */
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	printf("mvBlueLYNX-X\n");
+	if (get_cpu_family() == CPU_OMAP36XX)
+		setenv("mpurate", "1000");
+	else
+		setenv("mpurate", "600");
+
+	twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+	mvblx_init_fpga();
+
+	mac_read_from_eeprom();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	/* Configure GPMC registers */
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 139 as output pin */
+	writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+	/* Now send a pulse on the GPIO pin */
+	writel(GPIO11, &gpio5_base->setdataout);
+	udelay(1);
+	writel(GPIO11, &gpio5_base->cleardataout);
+	udelay(1);
+	writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
+int overwrite_console(void)
+{
+	/* return TRUE if console should be overwritten */
+	return 0;
+}
+
+#endif /* CONFIG_CMD_NET */

board/matrix_vision/mvblx/mvblx.h

@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"OMAP3 mvBlueLYNX-X camera",
+	"no NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M4)) /*GPIO_41*/\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO_42*/\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO_43*/\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO54*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO55*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTU | EN  | M4)) /*GPIO56*/\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO57*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M4)) /*GPIO58*/\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IEN  | PTU | EN  | M4)) /*GPIO60*/\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M4)) /*GPIO61*/\
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTU | EN  | M4)) /*GPIO62*/\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IDIS  | PTU | EN  | M4)) /*GPIO65*/\
+ /*DSS*/\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M4)) /*not_used*/\
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+	MUX_VAL(CP(MMC1_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT5),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | DIS  | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | DIS  | M0)) /*MMC2_CLK*/\
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) /*MMC2_CMD*/\
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT0*/\
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT1*/\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT2*/\
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT3*/\
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_136*/\
+	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_138*/\
+	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) /*GPIO_150*/ \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+	MUX_VAL(CP(MCBSP1_FSR),		(IEN | PTU | EN  | M4)) /*GPIO_157*/\
+	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
+	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
+	MUX_VAL(CP(MCSPI1_CLK),		(IDIS  | PTU | DIS  | M4)) /*GPIO_171*/\
+	MUX_VAL(CP(MCSPI1_SIMO),	(IDIS  | PTU | DIS  | M4)) /*GPIO_172*/\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IDIS  | PTU | DIS  | M4)) /*GPIO_173*/\
+	MUX_VAL(CP(MCSPI1_CS0),		(IDIS  | PTD | DIS  | M4)) /*GPIO_174*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IDIS  | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M0)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS  | PTD | DIS | M4)) /*GPIO_10*/\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS  | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN | PTU | EN | M4)) /*GPIO_24*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_26*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_27*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_28*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
+	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
+	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
+	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
+	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
+	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
+	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
+	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
+	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
+	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
+	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
+	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
+	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
+	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
+	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
+	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
+	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
+	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
+	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
+	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
+	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
+	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
+	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
+	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
+	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
+	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
+	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
+	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
+	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
+	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
+	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
+	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
+	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
+
+#endif

board/matrix_vision/mvblx/sys_eeprom.c

@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+	u8 id[16];		/* 0x01 - 0x0F Type e.g. 100wG-5111 */
+	u8 sn[10];		/* 0x10 - 0x19 Serial Number */
+	u8 date[6];		/* 0x1A - 0x1F Build Date */
+	u8 mac[6];		/* 0x20 - 0x25 MAC address  */
+	u8 reserved[10];/* 0x26 - 0x2f reserved */
+	u32 crc;        /* x+1         CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+	unsigned int crc;
+	char safe_string[16];
+
+#ifdef DEBUG
+	int i;
+#endif
+	u8 *p;
+
+	/* ID */
+	strncpy(safe_string, (char *)e.id, sizeof(e.id));
+	safe_string[sizeof(e.id)-1] = 0;
+	printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+	/* Serial number */
+	strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+	safe_string[sizeof(e.sn)-1] = 0;
+	printf("SN: %s\n", safe_string);
+
+	/* Build date, BCD date values, as YYMMDDhhmmss */
+	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+		e.date[0], e.date[1], e.date[2],
+		e.date[3] & 0x7F, e.date[4], e.date[5],
+		e.date[3] & 0x80 ? "PM" : "");
+
+	/* Show MAC address  */
+	p = e.mac;
+	printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+		p[0], p[1], p[2], p[3],	p[4], p[5]);
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+	if (crc == be32_to_cpu(e.crc))
+		printf("CRC: %08x\n", be32_to_cpu(e.crc));
+	else
+		printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+	for (i = 0; i < sizeof(e); i++) {
+		if ((i % 16) == 0)
+			printf("%02X: ", i);
+		printf("%02X ", ((u8 *)&e)[i]);
+		if (((i % 16) == 15) || (i == sizeof(e) - 1))
+			printf("\n");
+	}
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+	int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	if (has_been_read)
+		return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		(uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+	show_eeprom();
+#endif
+
+	has_been_read = (ret == 0) ? 1 : 0;
+
+	return ret;
+}
+
+/**
+ *  update_crc - update the CRC
+ *
+ *  This function should be called after each update to the EEPROM structure,
+ *  to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+	u32 crc;
+
+	crc = crc32(0, (void *)&e, sizeof(e) - 4);
+	e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+	int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	unsigned int bus;
+#endif
+
+	update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	bus = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+	ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		(uchar *)&e, sizeof(e));
+
+	if (!ret) {
+		/* Verify the write by reading back the EEPROM and comparing */
+		struct eeprom e2;
+#ifdef DEBUG
+		printf("%s verifying...\n", __func__);
+#endif
+		ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+			(uchar *)&e2, sizeof(e2));
+
+		if (!ret && memcmp(&e, &e2, sizeof(e)))
+			ret = -1;
+	}
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	i2c_set_bus_num(bus);
+#endif
+
+	if (ret) {
+		printf("Programming failed.\n");
+		has_been_read = 0;
+		return -1;
+	}
+
+	printf("Programming passed.\n");
+	return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+	if ((p >= '0') && (p <= '9'))
+		return p - '0';
+
+	if ((p >= 'A') && (p <= 'F'))
+		return (p - 'A') + 10;
+
+	if ((p >= 'a') && (p <= 'f'))
+		return (p - 'a') + 10;
+
+	return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+	unsigned int i;
+
+	if (strlen(string) != 12) {
+		printf("Usage: mac date YYMMDDhhmmss\n");
+		return;
+	}
+
+	for (i = 0; i < 6; i++)
+		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+	update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+	char *p = (char *) string;
+	unsigned int i;
+
+	for (i = 0; *p && (i < 6); i++) {
+		e.mac[i] = simple_strtoul(p, &p, 16);
+		if (*p == ':')
+			p++;
+	}
+
+	update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd;
+
+	if (argc == 1) {
+		show_eeprom();
+		return 0;
+	}
+
+	cmd = argv[1][0];
+
+	if (cmd == 'r') {
+#ifdef DEBUG
+		printf("%s read\n", __func__);
+#endif
+		read_eeprom();
+		return 0;
+	}
+
+	if (argc == 2) {
+		switch (cmd) {
+		case 's':	/* save */
+#ifdef DEBUG
+			printf("%s save\n", __func__);
+#endif
+			prog_eeprom();
+			break;
+		default:
+			return cmd_usage(cmdtp);
+		}
+
+		return 0;
+	}
+
+	/* We know we have at least one parameter  */
+
+	switch (cmd) {
+	case 'n':	/* serial number */
+#ifdef DEBUG
+		printf("%s serial number\n", __func__);
+#endif
+		memset(e.sn, 0, sizeof(e.sn));
+		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+		update_crc();
+		break;
+	case 'd':	/* date BCD format YYMMDDhhmmss */
+		set_date(argv[2]);
+		break;
+	case 'e':	/* errata */
+		printf("mac errata not implemented\n");
+		break;
+	case 'i':	/* id */
+		memset(e.id, 0, sizeof(e.id));
+		strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+		update_crc();
+		break;
+	case 'p':	/* ports */
+		printf("mac ports not implemented (always 1 port)\n");
+		break;
+	case '0' ... '9':
+		/* we only have "mac 0" but any digit can be used here */
+		set_mac_address(argv[2]);
+		break;
+	case 'h':	/* help */
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+	u32 crc, crc_offset = offsetof(struct eeprom, crc);
+	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+	if (read_eeprom()) {
+		printf("EEPROM Read failed.\n");
+		return -1;
+	}
+
+	crc = crc32(0, (void *)&e, crc_offset);
+	crcp = (void *)&e + crc_offset;
+	if (crc != be32_to_cpu(*crcp)) {
+		printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+			be32_to_cpu(e.crc));
+		return -1;
+	}
+
+	if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+		memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+		char ethaddr[9];
+
+		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+			e.mac[0],
+			e.mac[1],
+			e.mac[2],
+			e.mac[3],
+			e.mac[4],
+			e.mac[5]);
+		/* Only initialize environment variables that are blank
+		 * (i.e. have not yet been set)
+		 */
+		if (!getenv("ethaddr"))
+			setenv("ethaddr", ethaddr);
+	}
+
+	if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+		memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+		char serial_num[12];
+
+		strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+		/* Only initialize environment variables that are blank
+		 * (i.e. have not yet been set)
+		 */
+		if (!getenv("serial#"))
+			setenv("serial#", serial_num);
+	}
+
+	/* TODO should I calculate CRC here? */
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial = getenv("serial#");
+
+	if (serial && (strlen(serial) > 3)) {
+		/* use the numerical part of the serial number LXnnnnnn */
+		serialnr->high = 0;
+		serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif

board/samsung/origen/Makefile

@@ -41,7 +41,7 @@ OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 ALL	+=$(obj).depend $(LIB)
 
 ifdef CONFIG_SPL_BUILD
-ALL	+= tools/mk$(BOARD)spl.exe
+ALL	+= $(OBJTREE)/tools/mk$(BOARD)spl
 endif
 
 all:	$(ALL)
@@ -50,8 +50,8 @@ $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
 ifdef CONFIG_SPL_BUILD
-tools/mk$(BOARD)spl.exe:	tools/mkv310_image.c
-	$(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe
+$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
+	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
 endif
 
 #########################################################################

board/samsung/smdkv310/Makefile

@@ -26,16 +26,33 @@ LIB	= $(obj)lib$(BOARD).o
 
 SOBJS	:= mem_setup.o
 SOBJS	+= lowlevel_init.o
+ifndef CONFIG_SPL_BUILD
 COBJS	+= smdkv310.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+COBJS	+= mmc_boot.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
-all:	 $(obj).depend $(LIB)
+ALL	:=	 $(obj).depend $(LIB)
+
+ifdef CONFIG_SPL_BUILD
+ALL	+= $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
+all:	$(ALL)
 
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl:	tools/mkv310_image.c
+	$(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
 #########################################################################
 
 # defines $(obj).depend target

mmc_spl/board/samsung/smdkv310/mmc_boot.c → board/samsung/smdkv310/mmc_boot.c

@@ -23,15 +23,16 @@
 #include<common.h>
 #include<config.h>
 
-typedef u32(*copy_sd_mmc_to_mem) \
-	(u32 start_block, u32 block_count, u32 *dest_addr);
-
-
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* API (Data transfer from mmc to ram)
+*/
 void copy_uboot_to_ram(void)
 {
-	copy_sd_mmc_to_mem copy_bl2 = (copy_sd_mmc_to_mem)(0x00002488);
-	copy_bl2(BL2_START_OFFSET,\
-		BL2_SIZE_BLOC_COUNT, (u32 *)CONFIG_SYS_TEXT_BASE);
+	u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR;
+
+	copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
 }
 
 void board_init_f(unsigned long bootflag)

board/samsung/smdkv310/smdkv310.c

@@ -57,7 +57,6 @@ int board_init(void)
 
 	smc9115_pre_init();
 
-	gd->bd->bi_arch_number = MACH_TYPE_SMDKV310;
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 	return 0;
 }
@@ -75,13 +74,17 @@ int dram_init(void)
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+							PHYS_SDRAM_1_SIZE);
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+							PHYS_SDRAM_2_SIZE);
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+							PHYS_SDRAM_3_SIZE);
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+							PHYS_SDRAM_4_SIZE);
 }
 
 int board_eth_init(bd_t *bis)

board/samsung/universal_c210/universal.c

@@ -27,6 +27,7 @@
 #include <asm/arch/adc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,6 +58,10 @@ int board_init(void)
 	check_hw_revision();
 	printf("HW Revision:\t0x%x\n", board_rev);
 
+#if defined(CONFIG_PMIC)
+	pmic_init();
+#endif
+
 	return 0;
 }
 

board/syteco/jadecpu/jadecpu.c

@@ -40,7 +40,6 @@ int board_init(void)
 	writel(0x00000010, &ccnt->cmux_md);
 
 	gd->flags = 0;
-	gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
 	gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
 
 	icache_enable();

board/ti/evm/evm.c

@@ -217,7 +217,22 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR	"ethaddr"
+
+	struct eth_device *dev;
+	uchar eth_addr[6];
+
 	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+		dev = eth_get_dev_by_index(0);
+		if (dev) {
+			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+		} else {
+			printf("omap3evm: Couldn't get eth device\n");
+			rc = -1;
+		}
+	}
 #endif
 	return rc;
 }

board/ttcontrol/vision2/vision2.c

@@ -31,7 +31,6 @@
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <pmic.h>
@@ -44,8 +43,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static u32 system_rev;
-
 static struct fb_videomode nec_nl6448bc26_09c = {
 	"NEC_NL6448BC26-09C",
 	60,	/* Refresh */
@@ -151,13 +148,6 @@ static void init_drive_strength(void)
 		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 }
 
-u32 get_board_rev(void)
-{
-	system_rev = get_cpu_rev();
-
-	return system_rev;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,

boards.cfg

@@ -42,6 +42,8 @@ imx31_litekit                arm         arm1136     -                   logicpd
 imx31_phycore                arm         arm1136     -                   -              mx31
 imx31_phycore_eet            arm         arm1136     imx31_phycore       -              mx31         imx31_phycore:IMX31_PHYCORE_EET
 mx31pdk                      arm         arm1136     -                   freescale      mx31         mx31pdk:NAND_U_BOOT
+tt01                         arm         arm1136     -                   hale           mx31
+flea3                        arm         arm1136     -                   CarMediaLab    mx35
 mx35pdk                      arm         arm1136     -                   freescale      mx35
 omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
@@ -119,6 +121,7 @@ pm9263                       arm         arm926ejs   pm9263              ronetix
 pm9g45                       arm         arm926ejs   pm9g45              ronetix        at91        pm9g45:AT91SAM9G45
 da830evm                     arm         arm926ejs   da8xxevm            davinci        davinci
 da850evm                     arm         arm926ejs   da8xxevm            davinci        davinci
+cam_enc_4xx                  arm         arm926ejs   cam_enc_4xx         ait            davinci     cam_enc_4xx
 hawkboard                    arm         arm926ejs   da8xxevm            davinci        davinci
 hawkboard_nand               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:NAND_U_BOOT
 hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
@@ -132,7 +135,7 @@ davinci_schmoogie            arm         arm926ejs   schmoogie           davinci
 davinci_sffsdr               arm         arm926ejs   sffsdr              davinci        davinci
 davinci_sonata               arm         arm926ejs   sonata              davinci        davinci
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI
-km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood
+km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_RECONFIG_XLX
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
 portl2                       arm         arm926ejs   km_arm              keymile        kirkwood
 inetspace_v2                 arm         arm926ejs   netspace_v2         LaCie          kirkwood    netspace_v2:INETSPACE_V2
@@ -181,8 +184,11 @@ am3517_evm                   arm         armv7       am3517evm           logicpd
 dig297                       arm         armv7       dig297              comelit        omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
 omap3_zoom2                  arm         armv7       zoom2               logicpd        omap3
+omap3_mvblx                  arm         armv7       mvblx               matrix_vision  omap3
 omap3_beagle                 arm         armv7       beagle              ti             omap3
 omap3_evm                    arm         armv7       evm                 ti             omap3
+omap3_evm_quick_mmc          arm         armv7       evm                 ti             omap3
+omap3_evm_quick_nand         arm         armv7       evm                 ti             omap3
 omap3_sdp3430                arm         armv7       sdp3430             ti             omap3
 devkit8000                   arm         armv7       devkit8000          timll          omap3
 omap4_panda                  arm         armv7       panda               ti             omap4

doc/README.SPL

@@ -63,3 +63,5 @@ CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
 CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
 CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
 CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
+CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
+CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)

doc/README.davinci.nand_spl

@@ -0,0 +1,141 @@
+With this approach, we don't need the UBL any more on DaVinci boards.
+A "make boardname" will compile a u-boot.ubl, with UBL Header, which is
+needed for the RBL to find the "UBL", which actually is a  UBL-compatible
+header, nand spl code and u-boot code.
+
+
+As the RBL uses another read function as the "standard" u-boot,
+we need a command, which switches between this two read/write
+functions, so we can write the UBL header and the spl
+code in a format, which the RBL can read. This is realize
+(at the moment in board specific code) in the u-boot command
+nandrbl
+
+nandrbl without arguments returns actual mode (rbl or uboot).
+with nandrbl mode (mode = "rbl" or "uboot") you can switch
+between the two NAND read/write modes.
+
+
+To set up mkimage you need a config file for mkimage, example:
+board/ait/cam_enc_4xx/ublimage.cfg
+
+For information about the configuration please see:
+doc/README.ublimage
+
+Example for the cam_enc_4xx board:
+On the cam_enc_4xx board we have a NAND flash with blocksize = 0x20000 and
+pagesize = 0x800, so the u-boot.ubl image (which you get with:
+"make cam_enc_4xx") looks like this:
+
+00000000  00 ed ac a1 20 00 00 00  06 00 00 00 05 00 00 00  |.... ...........|
+00000010  00 00 00 00 20 00 00 00  ff ff ff ff ff ff ff ff  |.... ...........|
+00000020  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
+*
+00000800  14 00 00 ea 14 f0 9f e5  10 f0 9f e5 0c f0 9f e5  |................|
+00000810  08 f0 9f e5 04 f0 9f e5  00 f0 9f e5 04 f0 1f e5  |................|
+00000820  00 01 00 00 78 56 34 12  78 56 34 12 78 56 34 12  |....xV4.xV4.xV4.|
+[...]
+*
+00001fe0  00 00 00 00 00 00 00 00  ff ff ff ff ff ff ff ff  |................|
+00001ff0  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
+*
+00003800  14 00 00 ea 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
+00003810  14 f0 9f e5 14 f0 9f e5  14 f0 9f e5 14 f0 9f e5  |................|
+00003820  80 01 08 81 e0 01 08 81  40 02 08 81 a0 02 08 81  |........@.......|
+
+In the first "page" of the image, we have the UBL Header, needed for
+the RBL to find the spl code.
+
+The spl code starts in the second "page" of the image, with a size
+defined by:
+
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+After the spl code, there comes the "real" u-boot code
+@ (6 + 1) * pagesize = 0x3800
+
+------------------------------------------------------------------------
+Setting up spl code:
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER	5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((CONFIG_SYS_NROF_UBL_HEADER * \
+					CONFIG_SYS_NAND_BLOCK_SIZE) + \
+					(CONFIG_SYS_NROF_PAGES_NAND_SPL) * \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+------------------------------------------------------------------------
+
+Burning into NAND:
+
+step 1:
+The RBL searches from Block n ( n = 1..24) on page 0 for valid UBL
+Headers, so you have to burn the UBL header page from the u-boot.ubl
+image to the blocks, you want to have the UBL header.
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl rbl"
+
+step 2:
+You need to setup in the ublimage.cfg, where the RBL can find the spl
+code, and how big it is.
+
+!! RBL always starts reading from page 0 !!
+
+For the AIT board, we have:
+PAGES		6
+START_BLOCK	5
+
+So we need to copy the spl code to block 5 page 0
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl rbl"
+
+step 3:
+You need to copy the u-boot image to the block/page
+where the spl code reads it (CONFIG_SYS_NAND_U_BOOT_OFFS)
+!! Don;t forget to switch to rbl nand read/write functions with
+   "nandrbl uboot", which is default.
+
+On the cam_enc_4xx board it is:
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0xc0000)
+
+-> this results in following NAND usage on the cam_enc_4xx board:
+
+addr
+
+20000		possible UBL Header
+40000		possible UBL Header
+60000		possible UBL Header
+80000		possilbe UBL Header
+a0000		spl code
+c0000		u-boot code
+
+The above steps are executeed through the following environment vars:
+(using 80000 as address for the UBL header)
+
+pagesz=800
+uboot=/tftpboot/cam_enc_4xx/u-boot.ubl
+load=tftp 80000000 ${uboot}
+writeheader nandrbl rbl;nand erase 80000 ${pagesz};nand write 80000000 80000 ${pagesz};nandrbl uboot
+writenand_spl nandrbl rbl;nand erase a0000 3000;nand write 80000800 a0000 3000;nandrbl uboot
+writeuboot nandrbl uboot;nand erase c0000 5d000;nand write 80003800 c0000 5d000
+update=run load writeheader writenand_spl writeuboot
+
+If you do a "run load update" u-boot, spl + ubl header
+are magically updated ;-)
+
+Note:
+- There seem to be a bug in the RBL code (at least on my HW),
+  In the UBL block, I can set the page to values != 0, so it
+  is possible to burn step 1 and step 2 in one step into the
+  flash, but the RBL ignores the page settings, so I have to
+  burn the UBL Header to a page 0 and the spl code to
+  a page 0 ... :-(
+- If we make the nand read/write functions in the RBL equal to
+  the functions in u-boot (as I have no RBL code, it is only
+  possible in u-boot), we could burn the complete image in
+  one step ... that would be nice ...

doc/README.omap3

@@ -68,6 +68,11 @@ make
 make cm_t35_config
 make
 
+* BlueLYNX-X:
+
+make omap3_mvblx_config
+make
+
 Custom commands
 ===============
 

drivers/i2c/mxc_i2c.c

@@ -37,6 +37,7 @@
 
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <i2c.h>
 
 struct mxc_i2c_regs {
 	uint32_t	iadr;
@@ -73,6 +74,10 @@ struct mxc_i2c_regs {
 #define I2C_BASE        I2C2_BASE_ADDR
 #elif defined(CONFIG_SYS_I2C_MX35_PORT1)
 #define I2C_BASE	I2C_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
+#define I2C_BASE	I2C2_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
+#define I2C_BASE	I2C3_BASE_ADDR
 #else
 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
 #endif
@@ -95,16 +100,14 @@ static u16 i2c_clk_div[50][2] = {
 	{ 3072,	0x1E }, { 3840,	0x1F }
 };
 
-static u8 clk_div;
-
 /*
  * Calculate and set proper clock divider
  */
-static void i2c_imx_set_clk(unsigned int rate)
+static uint8_t i2c_imx_get_clk(unsigned int rate)
 {
-	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int i2c_clk_rate;
 	unsigned int div;
+	u8 clk_div;
 
 #if defined(CONFIG_MX31)
 	struct clock_control_regs *sc_regs =
@@ -127,7 +130,7 @@ static void i2c_imx_set_clk(unsigned int rate)
 			;
 
 	/* Store divider value */
-	writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+	return clk_div;
 }
 
 /*
@@ -146,7 +149,13 @@ void i2c_reset(void)
  */
 void i2c_init(int speed, int unused)
 {
-	i2c_imx_set_clk(speed);
+	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+	u8 clk_idx = i2c_imx_get_clk(speed);
+	u8 idx = i2c_clk_div[clk_idx][1];
+
+	/* Store divider value */
+	writeb(idx, &i2c_regs->ifdr);
+
 	i2c_reset();
 }
 
@@ -164,6 +173,13 @@ int i2c_set_bus_speed(unsigned int speed)
  */
 unsigned int i2c_get_bus_speed(void)
 {
+	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+	u8 clk_idx = readb(&i2c_regs->ifdr);
+	u8 clk_div;
+
+	for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
+		;
+
 	return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
 }
 
@@ -232,8 +248,12 @@ int i2c_imx_start(void)
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 	unsigned int temp = 0;
 	int result;
+	int speed = i2c_get_bus_speed();
+	u8 clk_idx = i2c_imx_get_clk(speed);
+	u8 idx = i2c_clk_div[clk_idx][1];
 
-	writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr);
+	/* Store divider value */
+	writeb(idx, &i2c_regs->ifdr);
 
 	/* Enable I2C controller */
 	writeb(0, &i2c_regs->i2sr);
@@ -306,11 +326,10 @@ int i2c_imx_set_chip_addr(uchar chip, int read)
 int i2c_imx_set_reg_addr(uint addr, int alen)
 {
 	struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-	int ret;
-	int i;
+	int ret = 0;
 
-	for (i = 0; i < (8 * alen); i += 8) {
-		writeb((addr >> i) & 0xff, &i2c_regs->i2dr);
+	while (alen--) {
+		writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
 
 		ret = i2c_imx_trx_complete();
 		if (ret)

drivers/misc/pmic_fsl.c

@@ -29,10 +29,7 @@
 #if defined(CONFIG_PMIC_SPI)
 static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
 {
-	if ((val == NULL) && (write))
-		return *val & ~(1 << 31);
-	else
-		return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
+	return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
 }
 #endif
 

drivers/misc/pmic_spi.c

@@ -76,8 +76,7 @@ static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
 	}
 
 	if (write) {
-		pmic_tx = p->hw.spi.prepare_tx(0, NULL, write);
-		pmic_tx &= ~(1 << 31);
+		pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
 		tmp = cpu_to_be32(pmic_tx);
 		if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
 			pmic_spi_flags)) {

drivers/mtd/nand/Makefile

@@ -30,6 +30,9 @@ ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_SPL_NAND_SIMPLE
 COBJS-y += nand_spl_simple.o
 endif
+ifdef CONFIG_SPL_NAND_LOAD
+COBJS-y	+= nand_spl_load.o
+endif
 else
 COBJS-y += nand.o
 COBJS-y += nand_bbt.o

drivers/mtd/nand/nand_spl_load.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+	int ret;
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	/*
+	 * Load U-Boot image from NAND into RAM
+	 */
+	ret =  nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			CONFIG_SYS_NAND_U_BOOT_SIZE,
+		(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+
+#ifdef CONFIG_NAND_ENV_DST
+	ret =  nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		(void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+	ret =  nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+		(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+	(*uboot)();
+}

drivers/mtd/nand/nand_spl_simple.c

@@ -140,6 +140,47 @@ static int nand_is_bad_block(int block)
 	return 0;
 }
 
+#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	u_char *ecc_calc;
+	u_char *ecc_code;
+	u_char *oob_data;
+	int i;
+	int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+	int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+	int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
+	uint8_t *p = dst;
+	int stat;
+
+	/*
+	 * No malloc available for now, just use some temporary locations
+	 * in SDRAM
+	 */
+	ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
+	ecc_code = ecc_calc + 0x100;
+	oob_data = ecc_calc + 0x200;
+
+	nand_command(block, page, 0, NAND_CMD_READOOB);
+	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	nand_command(block, page, 0, NAND_CMD_READ0);
+
+	/* Pick the ECC bytes out of the oob data */
+	for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
+		ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+		this->ecc.hwctl(&mtd, NAND_ECC_READ);
+		this->read_buf(&mtd, p, eccsize);
+		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+		stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+	}
+
+	return 0;
+}
+#else
 static int nand_read_page(int block, int page, void *dst)
 {
 	struct nand_chip *this = mtd.priv;
@@ -186,6 +227,7 @@ static int nand_read_page(int block, int page, void *dst)
 
 	return 0;
 }
+#endif
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
@@ -230,7 +272,6 @@ void nand_init(void)
 	mtd.priv = &nand_chip;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
-	nand_chip.options = 0;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)

drivers/net/davinci_emac.c

@@ -53,6 +53,11 @@ unsigned int	emac_dbg = 0;
 #define emac_gigabit_enable(phy_addr)	/* no gigabit to enable */
 #endif
 
+#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
+#define CONFIG_SYS_EMAC_TI_CLKDIV	((EMAC_MDIO_BUS_FREQ / \
+		EMAC_MDIO_CLOCK_FREQ) - 1)
+#endif
+
 static void davinci_eth_mdio_enable(void);
 
 static int gen_init_phy(int phy_addr);
@@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void)
 {
 	u_int32_t	clkdiv;
 
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 
 	writel((clkdiv & 0xff) |
 	       MDIO_CONTROL_ENABLE |
@@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 #endif
 
 	/* Init MDIO & get link state */
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+	clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
 	writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
 	       &adap_mdio->CONTROL);
 
@@ -809,7 +814,7 @@ int davinci_emac_initialize(void)
 			phy[i].auto_negotiate = gen_auto_negotiate;
 		}
 
-		debug("Ethernet PHY: %s\n", phy.name);
+		debug("Ethernet PHY: %s\n", phy[i].name);
 
 		miiphy_register(phy[i].name, davinci_mii_phy_read,
 						davinci_mii_phy_write);

drivers/net/mvgbe.c

@@ -37,6 +37,7 @@
 #include <asm/types.h>
 #include <asm/system.h>
 #include <asm/byteorder.h>
+#include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>

drivers/rtc/Makefile

@@ -50,7 +50,7 @@ COBJS-$(CONFIG_RTC_M41T62) += m41t62.o
 COBJS-$(CONFIG_RTC_M41T94) += m41t94.o
 COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o
 COBJS-$(CONFIG_RTC_MAX6900) += max6900.o
-COBJS-$(CONFIG_RTC_MC13783) += mc13783-rtc.o
+COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
 COBJS-$(CONFIG_RTC_MC146818) += mc146818.o
 COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
 COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o

drivers/rtc/mvrtc.c

@@ -28,6 +28,7 @@
 #include <common.h>
 #include <command.h>
 #include <rtc.h>
+#include <asm/io.h>
 #include "mvrtc.h"
 
 /* This RTC does not support century, so we assume 20 */

drivers/usb/host/ehci-mxc.c

@@ -120,7 +120,6 @@ int ehci_hcd_init(void)
 
 	udelay(80);
 
-	/* Take USB2 */
 	ehci = (struct usb_ehci *)(IMX_USB_BASE +
 		(0x200 * CONFIG_MXC_USB_PORT));
 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);

drivers/usb/musb/davinci.c

@@ -26,6 +26,10 @@
 #include "davinci.h"
 #include <asm/arch/hardware.h>
 
+#if !defined(CONFIG_DV_USBPHY_CTL)
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
+#endif
+
 /* MUSB platform configuration */
 struct musb_config musb_cfg = {
 	.regs		= (struct musb_regs *)MENTOR_USB0_BASE,
@@ -50,7 +54,7 @@ static u8 phy_on(void)
 	writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
 			USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
 #else
-	writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
+	writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
 #endif
 	timeout = musb_cfg.timeout;
 
@@ -78,6 +82,17 @@ static void phy_off(void)
 	writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
 }
 
+void __enable_vbus(void)
+{
+	/*
+	 *  nothing to do, vbus is handled through the cpu.
+	 *  Define this function in board code, if it is
+	 *  different on your board.
+	 */
+}
+void  enable_vbus(void)
+	__attribute__((weak, alias("__enable_vbus")));
+
 /*
  * This function performs Davinci platform specific initialization for usb0.
  */
@@ -86,9 +101,8 @@ int musb_platform_init(void)
 	u32  revision;
 
 	/* enable USB VBUS */
-#ifndef DAVINCI_DM365EVM
 	enable_vbus();
-#endif
+
 	/* start the on-chip USB phy and its pll */
 	if (!phy_on())
 		return -1;

drivers/video/Makefile

@@ -33,6 +33,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
+COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o

drivers/video/da8xx-fb.c

@@ -0,0 +1,846 @@
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "videomodes.h"
+#include <asm/arch/da8xx-fb.h>
+
+#define DRIVER_NAME "da8xx_lcdc"
+
+/* LCD Status Register */
+#define LCD_END_OF_FRAME1		(1 << 9)
+#define LCD_END_OF_FRAME0		(1 << 8)
+#define LCD_PL_LOAD_DONE		(1 << 6)
+#define LCD_FIFO_UNDERFLOW		(1 << 5)
+#define LCD_SYNC_LOST			(1 << 2)
+
+/* LCD DMA Control Register */
+#define LCD_DMA_BURST_SIZE(x)		((x) << 4)
+#define LCD_DMA_BURST_1			0x0
+#define LCD_DMA_BURST_2			0x1
+#define LCD_DMA_BURST_4			0x2
+#define LCD_DMA_BURST_8			0x3
+#define LCD_DMA_BURST_16		0x4
+#define LCD_END_OF_FRAME_INT_ENA	(1 << 2)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE	(1 << 0)
+
+/* LCD Control Register */
+#define LCD_CLK_DIVISOR(x)		((x) << 8)
+#define LCD_RASTER_MODE			0x01
+
+/* LCD Raster Control Register */
+#define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
+#define PALETTE_AND_DATA		0x00
+#define PALETTE_ONLY			0x01
+#define DATA_ONLY			0x02
+
+#define LCD_MONO_8BIT_MODE		(1 << 9)
+#define LCD_RASTER_ORDER		(1 << 8)
+#define LCD_TFT_MODE			(1 << 7)
+#define LCD_UNDERFLOW_INT_ENA		(1 << 6)
+#define LCD_PL_ENABLE			(1 << 4)
+#define LCD_MONOCHROME_MODE		(1 << 1)
+#define LCD_RASTER_ENABLE		(1 << 0)
+#define LCD_TFT_ALT_ENABLE		(1 << 23)
+#define LCD_STN_565_ENABLE		(1 << 24)
+
+/* LCD Raster Timing 2 Register */
+#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
+#define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
+#define LCD_SYNC_CTRL				(1 << 25)
+#define LCD_SYNC_EDGE				(1 << 24)
+#define LCD_INVERT_PIXEL_CLOCK			(1 << 22)
+#define LCD_INVERT_LINE_CLOCK			(1 << 21)
+#define LCD_INVERT_FRAME_CLOCK			(1 << 20)
+
+/* LCD Block */
+struct da8xx_lcd_regs {
+	u32	revid;
+	u32	ctrl;
+	u32	stat;
+	u32	lidd_ctrl;
+	u32	lidd_cs0_conf;
+	u32	lidd_cs0_addr;
+	u32	lidd_cs0_data;
+	u32	lidd_cs1_conf;
+	u32	lidd_cs1_addr;
+	u32	lidd_cs1_data;
+	u32	raster_ctrl;
+	u32	raster_timing_0;
+	u32	raster_timing_1;
+	u32	raster_timing_2;
+	u32	raster_subpanel;
+	u32	reserved;
+	u32	dma_ctrl;
+	u32	dma_frm_buf_base_addr_0;
+	u32	dma_frm_buf_ceiling_addr_0;
+	u32	dma_frm_buf_base_addr_1;
+	u32	dma_frm_buf_ceiling_addr_1;
+};
+
+#define LCD_NUM_BUFFERS	1
+
+#define WSI_TIMEOUT	50
+#define PALETTE_SIZE	256
+#define LEFT_MARGIN	64
+#define RIGHT_MARGIN	64
+#define UPPER_MARGIN	32
+#define LOWER_MARGIN	32
+
+#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+
+static struct da8xx_lcd_regs *da8xx_fb_reg_base;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice gpanel;
+static const struct da8xx_panel *lcd_panel;
+static struct fb_info *da8xx_fb_info;
+static int bits_x_pixel;
+
+static inline unsigned int lcdc_read(u32 *addr)
+{
+	return (unsigned int)readl(addr);
+}
+
+static inline void lcdc_write(unsigned int val, u32 *addr)
+{
+	writel(val, addr);
+}
+
+struct da8xx_fb_par {
+	u32			 p_palette_base;
+	unsigned char *v_palette_base;
+	dma_addr_t		vram_phys;
+	unsigned long		vram_size;
+	void			*vram_virt;
+	unsigned int		dma_start;
+	unsigned int		dma_end;
+	struct clk *lcdc_clk;
+	int irq;
+	unsigned short pseudo_palette[16];
+	unsigned int palette_sz;
+	unsigned int pxl_clk;
+	int blank;
+	int			vsync_flag;
+	int			vsync_timeout;
+};
+
+
+/* Variable Screen Information */
+static struct fb_var_screeninfo da8xx_fb_var = {
+	.xoffset = 0,
+	.yoffset = 0,
+	.transp = {0, 0, 0},
+	.nonstd = 0,
+	.activate = 0,
+	.height = -1,
+	.width = -1,
+	.pixclock = 46666,	/* 46us - AUO display */
+	.accel_flags = 0,
+	.left_margin = LEFT_MARGIN,
+	.right_margin = RIGHT_MARGIN,
+	.upper_margin = UPPER_MARGIN,
+	.lower_margin = LOWER_MARGIN,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_fix_screeninfo da8xx_fb_fix = {
+	.id = "DA8xx FB Drv",
+	.type = FB_TYPE_PACKED_PIXELS,
+	.type_aux = 0,
+	.visual = FB_VISUAL_PSEUDOCOLOR,
+	.xpanstep = 0,
+	.ypanstep = 1,
+	.ywrapstep = 0,
+	.accel = FB_ACCEL_NONE
+};
+
+static const struct display_panel disp_panel = {
+	QVGA,
+	16,
+	16,
+	COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+	&disp_panel,
+	.ac_bias		= 255,
+	.ac_bias_intrpt		= 0,
+	.dma_burst_sz		= 16,
+	.bpp			= 16,
+	.fdd			= 255,
+	.tft_alt_mode		= 0,
+	.stn_565_mode		= 0,
+	.mono_8bit_mode		= 0,
+	.invert_line_clock	= 1,
+	.invert_frm_clock	= 1,
+	.sync_edge		= 0,
+	.sync_ctrl		= 1,
+	.raster_order		= 0,
+};
+
+/* Enable the Raster Engine of the LCD Controller */
+static inline void lcd_enable_raster(void)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	if (!(reg & LCD_RASTER_ENABLE))
+		lcdc_write(reg | LCD_RASTER_ENABLE,
+			&da8xx_fb_reg_base->raster_ctrl);
+}
+
+/* Disable the Raster Engine of the LCD Controller */
+static inline void lcd_disable_raster(void)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	if (reg & LCD_RASTER_ENABLE)
+		lcdc_write(reg & ~LCD_RASTER_ENABLE,
+			&da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
+{
+	u32 start;
+	u32 end;
+	u32 reg_ras;
+	u32 reg_dma;
+
+	/* init reg to clear PLM (loading mode) fields */
+	reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+	reg_ras &= ~(3 << 20);
+
+	reg_dma  = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+
+	if (load_mode == LOAD_DATA) {
+		start    = par->dma_start;
+		end      = par->dma_end;
+
+		reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
+		reg_dma |= LCD_END_OF_FRAME_INT_ENA;
+
+#if (LCD_NUM_BUFFERS == 2)
+		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#else
+		reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+		lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+#endif
+
+	} else if (load_mode == LOAD_PALETTE) {
+		start    = par->p_palette_base;
+		end      = start + par->palette_sz - 1;
+
+		reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
+		reg_ras |= LCD_PL_ENABLE;
+
+		lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+	}
+
+	lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
+	lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+	/*
+	 * The Raster enable bit must be set after all other control fields are
+	 * set.
+	 */
+	lcd_enable_raster();
+}
+
+/* Configure the Burst Size of DMA */
+static int lcd_cfg_dma(int burst_size)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+	switch (burst_size) {
+	case 1:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
+		break;
+	case 2:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
+		break;
+	case 4:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
+		break;
+	case 8:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
+		break;
+	case 16:
+		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
+		break;
+	default:
+		return -EINVAL;
+	}
+	lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
+
+	return 0;
+}
+
+static void lcd_cfg_ac_bias(int period, int transitions_per_int)
+{
+	u32 reg;
+
+	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
+	reg |= LCD_AC_BIAS_FREQUENCY(period) |
+		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+}
+
+static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+}
+
+static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
+		int front_porch)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
+	reg |= ((back_porch & 0xff) << 24)
+	    | ((front_porch & 0xff) << 16)
+	    | ((pulse_width & 0x3f) << 10);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+}
+
+static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
+{
+	u32 reg;
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
+						LCD_MONO_8BIT_MODE |
+						LCD_MONOCHROME_MODE);
+
+	switch (cfg->p_disp_panel->panel_shade) {
+	case MONOCHROME:
+		reg |= LCD_MONOCHROME_MODE;
+		if (cfg->mono_8bit_mode)
+			reg |= LCD_MONO_8BIT_MODE;
+		break;
+	case COLOR_ACTIVE:
+		reg |= LCD_TFT_MODE;
+		if (cfg->tft_alt_mode)
+			reg |= LCD_TFT_ALT_ENABLE;
+		break;
+
+	case COLOR_PASSIVE:
+		if (cfg->stn_565_mode)
+			reg |= LCD_STN_565_ENABLE;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* enable additional interrupts here */
+	reg |= LCD_UNDERFLOW_INT_ENA;
+
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+
+	if (cfg->sync_ctrl)
+		reg |= LCD_SYNC_CTRL;
+	else
+		reg &= ~LCD_SYNC_CTRL;
+
+	if (cfg->sync_edge)
+		reg |= LCD_SYNC_EDGE;
+	else
+		reg &= ~LCD_SYNC_EDGE;
+
+	if (cfg->invert_line_clock)
+		reg |= LCD_INVERT_LINE_CLOCK;
+	else
+		reg &= ~LCD_INVERT_LINE_CLOCK;
+
+	if (cfg->invert_frm_clock)
+		reg |= LCD_INVERT_FRAME_CLOCK;
+	else
+		reg &= ~LCD_INVERT_FRAME_CLOCK;
+
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+
+	return 0;
+}
+
+static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
+		u32 bpp, u32 raster_order)
+{
+	u32 reg;
+
+	/* Set the Panel Width */
+	/* Pixels per line = (PPL + 1)*16 */
+	/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
+	width &= 0x3f0;
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
+	reg &= 0xfffffc00;
+	reg |= ((width >> 4) - 1) << 4;
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
+
+	/* Set the Panel Height */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
+	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+
+	/* Set the Raster Order of the Frame Buffer */
+	reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
+	if (raster_order)
+		reg |= LCD_RASTER_ORDER;
+	lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
+
+	switch (bpp) {
+	case 1:
+	case 2:
+	case 4:
+	case 16:
+		par->palette_sz = 16 * 2;
+		break;
+
+	case 8:
+		par->palette_sz = 256 * 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			      unsigned blue, unsigned transp,
+			      struct fb_info *info)
+{
+	struct da8xx_fb_par *par = info->par;
+	unsigned short *palette = (unsigned short *) par->v_palette_base;
+	u_short pal;
+	int update_hw = 0;
+
+	if (regno > 255)
+		return 1;
+
+	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
+		return 1;
+
+	if (info->var.bits_per_pixel == 8) {
+		red >>= 4;
+		green >>= 8;
+		blue >>= 12;
+
+		pal = (red & 0x0f00);
+		pal |= (green & 0x00f0);
+		pal |= (blue & 0x000f);
+
+		if (palette[regno] != pal) {
+			update_hw = 1;
+			palette[regno] = pal;
+		}
+	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+		red >>= (16 - info->var.red.length);
+		red <<= info->var.red.offset;
+
+		green >>= (16 - info->var.green.length);
+		green <<= info->var.green.offset;
+
+		blue >>= (16 - info->var.blue.length);
+		blue <<= info->var.blue.offset;
+
+		par->pseudo_palette[regno] = red | green | blue;
+
+		if (palette[0] != 0x4000) {
+			update_hw = 1;
+			palette[0] = 0x4000;
+		}
+	}
+
+	/* Update the palette in the h/w as needed. */
+	if (update_hw)
+		lcd_blit(LOAD_PALETTE, par);
+
+	return 0;
+}
+
+static void lcd_reset(struct da8xx_fb_par *par)
+{
+	/* Disable the Raster if previously Enabled */
+	lcd_disable_raster();
+
+	/* DMA has to be disabled */
+	lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
+	lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+}
+
+static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
+{
+	unsigned int lcd_clk, div;
+
+	/* Get clock from sysclk2 */
+	lcd_clk = clk_get(2);
+
+	div = lcd_clk / par->pxl_clk;
+	debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
+		lcd_clk, div, par->pxl_clk);
+
+	/* Configure the LCD clock divisor. */
+	lcdc_write(LCD_CLK_DIVISOR(div) |
+			(LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+}
+
+static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
+		const struct da8xx_panel *panel)
+{
+	u32 bpp;
+	int ret = 0;
+
+	lcd_reset(par);
+
+	/* Calculate the divider */
+	lcd_calc_clk_divider(par);
+
+	if (panel->invert_pxl_clk)
+		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
+			LCD_INVERT_PIXEL_CLOCK),
+			 &da8xx_fb_reg_base->raster_timing_2);
+	else
+		lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
+			~LCD_INVERT_PIXEL_CLOCK),
+			&da8xx_fb_reg_base->raster_timing_2);
+
+	/* Configure the DMA burst size. */
+	ret = lcd_cfg_dma(cfg->dma_burst_sz);
+	if (ret < 0)
+		return ret;
+
+	/* Configure the AC bias properties. */
+	lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
+
+	/* Configure the vertical and horizontal sync properties. */
+	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
+	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
+
+	/* Configure for disply */
+	ret = lcd_cfg_display(cfg);
+	if (ret < 0)
+		return ret;
+
+	if (QVGA != cfg->p_disp_panel->panel_type)
+		return -EINVAL;
+
+	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
+	    cfg->bpp >= cfg->p_disp_panel->min_bpp)
+		bpp = cfg->bpp;
+	else
+		bpp = cfg->p_disp_panel->max_bpp;
+	if (bpp == 12)
+		bpp = 16;
+	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
+				(unsigned int)panel->height, bpp,
+				cfg->raster_order);
+	if (ret < 0)
+		return ret;
+
+	/* Configure FDD */
+	lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
+		       (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
+
+	return 0;
+}
+
+static void lcdc_dma_start(void)
+{
+	struct da8xx_fb_par *par = da8xx_fb_info->par;
+	lcdc_write(par->dma_start,
+		&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+	lcdc_write(par->dma_end,
+		&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+	lcdc_write(0,
+		&da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+	lcdc_write(0,
+		&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+}
+
+static u32 lcdc_irq_handler(void)
+{
+	struct da8xx_fb_par *par = da8xx_fb_info->par;
+	u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
+	u32 reg_ras;
+
+	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		debug("LCD_SYNC_LOST\n");
+		lcd_disable_raster();
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+		lcd_enable_raster();
+		return LCD_SYNC_LOST;
+	} else if (stat & LCD_PL_LOAD_DONE) {
+		debug("LCD_PL_LOAD_DONE\n");
+		/*
+		 * Must disable raster before changing state of any control bit.
+		 * And also must be disabled before clearing the PL loading
+		 * interrupt via the following write to the status register. If
+		 * this is done after then one gets multiple PL done interrupts.
+		 */
+		lcd_disable_raster();
+
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+		/* Disable PL completion inerrupt */
+		reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
+		reg_ras &= ~LCD_PL_ENABLE;
+		lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
+
+		/* Setup and start data loading mode */
+		lcd_blit(LOAD_DATA, par);
+		return LCD_PL_LOAD_DONE;
+	} else {
+		lcdc_write(stat, &da8xx_fb_reg_base->stat);
+
+		if (stat & LCD_END_OF_FRAME0)
+			debug("LCD_END_OF_FRAME0\n");
+
+		lcdc_write(par->dma_start,
+			&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+		lcdc_write(par->dma_end,
+			&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+		par->vsync_flag = 1;
+		return LCD_END_OF_FRAME0;
+	}
+	return stat;
+}
+
+static u32 wait_for_event(u32 event)
+{
+	u32 timeout = 50000;
+	u32 ret;
+
+	do {
+		ret = lcdc_irq_handler();
+		udelay(1000);
+	} while (!(ret & event));
+
+	if (timeout <= 0) {
+		printf("%s: event %d not hit\n", __func__, event);
+		return -1;
+	}
+
+	return 0;
+
+}
+
+void *video_hw_init(void)
+{
+	struct da8xx_fb_par *par;
+	int ret;
+	u32 size;
+	char *p;
+
+	if (!lcd_panel) {
+		printf("Display not initialized\n");
+		return NULL;
+	}
+	gpanel.winSizeX = lcd_panel->width;
+	gpanel.winSizeY = lcd_panel->height;
+	gpanel.plnSizeX = lcd_panel->width;
+	gpanel.plnSizeY = lcd_panel->height;
+
+	switch (bits_x_pixel) {
+	case 24:
+		gpanel.gdfBytesPP = 4;
+		gpanel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		gpanel.gdfBytesPP = 2;
+		gpanel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	default:
+		gpanel.gdfBytesPP = 1;
+		gpanel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
+
+	da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
+
+	debug("Resolution: %dx%d %x\n",
+		gpanel.winSizeX,
+		gpanel.winSizeY,
+		lcd_cfg.bpp);
+
+	size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
+	da8xx_fb_info = malloc(size);
+	debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+
+	if (!da8xx_fb_info) {
+		printf("Memory allocation failed for fb_info\n");
+		return NULL;
+	}
+	memset(da8xx_fb_info, 0, size);
+	p = (char *)da8xx_fb_info;
+	da8xx_fb_info->par = p +  sizeof(struct fb_info);
+	debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
+
+	par = da8xx_fb_info->par;
+	par->pxl_clk = lcd_panel->pxl_clk;
+
+	if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
+		printf("lcd_init failed\n");
+		ret = -EFAULT;
+		goto err_release_fb;
+	}
+
+	/* allocate frame buffer */
+	par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
+	par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+
+	par->vram_virt = malloc(par->vram_size);
+
+	par->vram_phys = (dma_addr_t) par->vram_virt;
+	debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
+		(unsigned int)par->vram_size,
+		(unsigned int)par->vram_virt);
+	if (!par->vram_virt) {
+		printf("GLCD: malloc for frame buffer failed\n");
+		ret = -EINVAL;
+		goto err_release_fb;
+	}
+
+	gpanel.frameAdrs = (unsigned int)par->vram_virt;
+	da8xx_fb_info->screen_base = (char *) par->vram_virt;
+	da8xx_fb_fix.smem_start	= gpanel.frameAdrs;
+	da8xx_fb_fix.smem_len = par->vram_size;
+	da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
+
+	par->dma_start = par->vram_phys;
+	par->dma_end   = par->dma_start + lcd_panel->height *
+		da8xx_fb_fix.line_length - 1;
+
+	/* allocate palette buffer */
+	par->v_palette_base = malloc(PALETTE_SIZE);
+	if (!par->v_palette_base) {
+		printf("GLCD: malloc for palette buffer failed\n");
+		goto err_release_fb_mem;
+	}
+	memset(par->v_palette_base, 0, PALETTE_SIZE);
+	par->p_palette_base = (unsigned int)par->v_palette_base;
+
+	/* Initialize par */
+	da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+
+	da8xx_fb_var.xres = lcd_panel->width;
+	da8xx_fb_var.xres_virtual = lcd_panel->width;
+
+	da8xx_fb_var.yres         = lcd_panel->height;
+	da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
+
+	da8xx_fb_var.grayscale =
+	    lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
+	da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
+
+	da8xx_fb_var.hsync_len = lcd_panel->hsw;
+	da8xx_fb_var.vsync_len = lcd_panel->vsw;
+
+	/* Initialize fbinfo */
+	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
+	da8xx_fb_info->fix = da8xx_fb_fix;
+	da8xx_fb_info->var = da8xx_fb_var;
+	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
+	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
+				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+
+	/* Clear interrupt */
+	memset((void *)par->vram_virt, 0, par->vram_size);
+	lcd_disable_raster();
+	lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
+	debug("Palette at 0x%x size %d\n", par->p_palette_base,
+		par->palette_sz);
+	lcdc_dma_start();
+
+	/* Load a default palette */
+	fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
+
+	/* Check that the palette is loaded */
+	wait_for_event(LCD_PL_LOAD_DONE);
+
+	/* Wait until DMA is working */
+	wait_for_event(LCD_END_OF_FRAME0);
+
+	return (void *)&gpanel;
+
+err_release_fb_mem:
+	free(par->vram_virt);
+
+err_release_fb:
+	free(da8xx_fb_info);
+
+	return NULL;
+}
+
+void video_set_lut(unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
+{
+
+	return;
+}
+
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
+{
+	lcd_panel = panel;
+	bits_x_pixel = bits_pixel;
+}

include/configs/am335x_evm.h

@@ -32,6 +32,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 * 1024))
 #define CONFIG_SYS_PROMPT		"AM335X# "
 #define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
 #define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
 
 #define CONFIG_CMD_ASKENV

include/configs/cam_enc_4xx.h

@@ -0,0 +1,453 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM365
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_DAVINCI_DM365_EVM
+
+#define CONFIG_HOSTNAME			cam_enc_4xx
+
+#define	BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
+#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED		3000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x0
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/*  Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT		"2m(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	(0x800)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(0x20000)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE		0x0000020 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		12320
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE		0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28,			\
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		0x200
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE /	 \
+					 CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(40)
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_UBL_HEADER	5
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR	0x0
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0xc0000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+
+/*
+ * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
+ * done in board_init_f from c code.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
+/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
+/*
+ * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
+/* POST DIV 680/2 = 340Mhz  -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
+/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
+/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
+	| DV_DDR_PHY_EXT_STRBEN \
+	| DV_DDR_PHY_PWRDNEN \
+	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
+	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
+	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
+	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP  = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1     = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
+	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
+	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
+	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+	| (5 << DV_DDR_SDCR_CL_SHIFT) \
+	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
+	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
+	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR	0xff
+#define CONFIG_SYS_DM36x_AB1CR	0x40400204
+#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4	0x00002655
+
+/*
+ * Default environment settings
+ */
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0"		\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0"			\
+	"load=tftp ${u_boot_addr_r} ${uboot}\0"				\
+	"pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0"			\
+	"writeheader=nandrbl rbl;nand erase 80000 ${pagesz};"		\
+		"nand write ${u_boot_addr_r} 80000 ${pagesz};"		\
+		"nandrbl uboot\0"					\
+	"writenand_spl=nandrbl rbl;nand erase a0000 3000;"		\
+		"nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
+		" a0000 3000;nandrbl uboot\0"				\
+	"writeuboot=nandrbl uboot;"					\
+		"nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
+		 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE)			\
+		";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT)		\
+		" " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
+		xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"			\
+	"update=run load writenand_spl writeuboot\0"			\
+	"bootcmd=run bootcmd\0"						\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+				USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+#endif /* __CONFIG_H */

include/configs/dig297.h

@@ -32,6 +32,14 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_OMAP3_CPS
+#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
+#else
+#define MACH_TYPE_OMAP3_CPS 2751
+#endif
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+
 /*
  * High Level Configuration Options
  */

include/configs/ea20.h

@@ -28,7 +28,12 @@
  */
 #define CONFIG_DRIVER_TI_EMAC
 #define CONFIG_USE_SPIFLASH
+#define	CONFIG_SYS_USE_NAND
 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOARD_EARLY_INIT_F
+#define BOARD_LATE_INIT
+#define CONFIG_VIDEO
+#define CONFIG_PREBOOT
 
 /*
  * SoC Configuration
@@ -47,7 +52,7 @@
 /*
  * Memory Info
  */
-#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 4*1024*1024) /* malloc() len */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
@@ -67,7 +72,7 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
@@ -82,6 +87,13 @@
 #define CONFIG_SF_DEFAULT_SPEED		30000000
 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
 
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+
 /*
  * Network & Ethernet Configuration
  */
@@ -99,11 +111,22 @@
 #undef CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SIZE			(8 << 10)
-#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_OFFSET		0x80000
 #define CONFIG_ENV_SECT_SIZE		(64 << 10)
 #define CONFIG_SYS_NO_FLASH
 #endif
 
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#endif
+
 /*
  * U-Boot general configuration
  */
@@ -143,6 +166,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_I2C
 
 #ifndef CONFIG_DRIVER_TI_EMAC
 #undef CONFIG_CMD_NET
@@ -151,7 +175,8 @@
 #undef CONFIG_CMD_PING
 #endif
 
-#ifdef CONFIG_USE_NAND
+/* NAND Setup */
+#ifdef CONFIG_SYS_USE_NAND
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_CMD_NAND
@@ -163,8 +188,20 @@
 #define CONFIG_RBTREE
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
+
+#define CONFIG_NAND_DAVINCI
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
+/* SPI Flash */
 #ifdef CONFIG_USE_SPIFLASH
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_FLASH
@@ -173,7 +210,7 @@
 #define CONFIG_CMD_SAVEENV
 #endif
 
-#if !defined(CONFIG_USE_NAND) && \
+#if !defined(CONFIG_SYS_USE_NAND) && \
 	!defined(CONFIG_USE_NOR) && \
 	!defined(CONFIG_USE_SPIFLASH)
 #define CONFIG_ENV_IS_NOWHERE
@@ -187,4 +224,83 @@
 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 					GENERATED_GBL_DATA_SIZE)
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+
+#define CONFIG_HOSTNAME ea20
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"as=3\0"							\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"rfsbargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=${serverip}:${rfsbpath}\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"mtdids=nand0=davinci_nand.0\0"					\
+	"mtdparts=mtdparts=davinci_nand.0:8m(Settings),8m(aKernel),"	\
+	"8m(bKernel),76m(aRootfs),76m(bRootfs),-(MassSD)\0"		\
+	"nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc "	\
+	"ubi.mtd=${as} root=ubi0:rootfs\0"				\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}n8\0"		\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"addmem=setenv bootargs ${bootargs} mem=${memory}\0"		\
+	"consoledev=ttyS0\0"						\
+	"loadaddr=c0000014\0"						\
+	"memory=32M\0"							\
+	"kernel_addr_r=c0700000\0"					\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	"flash_self=run ramargs addip addtty addmtd addmisc addmem;"	\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;"	\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
+		"run nfsargs addip addtty addmtd addmisc addmem;"	\
+		"bootm ${kernel_addr_r}\0"                              \
+	"net_rfsb=tftp ${kernel_addr_r} ${bootfile}; "                  \
+		"run rfsbargs addip addtty addmtd addmisc addmem; "     \
+		"bootm ${kernel_addr_r}\0"                              \
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"nand_nand=ubi part nand0,${as};ubifsmount rootfs;"             \
+		"ubifsload ${kernel_addr_r} /boot/uImage;"              \
+		"ubifsumount; run nandargs addip addtty "               \
+		"addmtd addmisc addmem;bootm ${kernel_addr_r}\0"        \
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"load_magic=if sf probe 0;then sf "                             \
+		"read c0000000 0x10000 0x60000;fi\0"                    \
+	"load_nand=ubi part nand0,${as};ubifsmount rootfs;"             \
+		"if ubifsload c0000014 /boot/u-boot.bin;"               \
+		"then mw c0000008 ${filesize};else echo Error reading " \
+		"u-boot from nand!;fi\0"                                \
+	"load_net=if sf probe 0;then sf read c0000000 0x10000 0x60000;"	\
+		"tftp c0000014 ${u-boot};"				\
+		"mw c0000008 ${filesize};"				\
+		"fi\0"		                                        \
+	"upd=if sf probe 0;then sf erase 10000 60000;"		        \
+		"sf write c0000000 10000 60000;"			\
+		"fi\0"							\
+	"ubootupd_net=if run load_net;then echo Updating u-boot;"       \
+		"if run upd; then echo U-Boot updated;"			\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"ubootupd_nand=echo run load_magic,run load_nand,run upd;\0"    \
+	"bootcmd=run net_nfs\0"
+
 #endif /* __CONFIG_H */