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@@ -64,7 +64,6 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
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# bit31-30: 01
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# bit31-30: 01
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DATA 0xFFD01404 0x36343000 # DDR Controller Control Low
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DATA 0xFFD01404 0x36343000 # DDR Controller Control Low
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- 0x38543000
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# bit 3-0: 0 reserved
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# bit 3-0: 0 reserved
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# bit 4: 0=addr/cmd in smame cycle
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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@@ -170,7 +169,7 @@ DATA 0xFFD0149C 0x0000E90F # CPU ODT Control
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# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
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# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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-#bit0=1, enable DDR init upon this register write
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+# bit0=1, enable DDR init upon this register write
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# End of Header extension
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# End of Header extension
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DATA 0x0 0x0
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DATA 0x0 0x0
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