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@@ -207,6 +207,52 @@ static int receive_bytes(uchar chip, char *buf, int len)
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return 0;
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}
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+#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
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+
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+#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
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+#define FDR432(x) (u8) ((x & 0x1C) >> 2)
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+/*
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+ * Reset any i2c devices that may have been interrupted during a system reset.
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+ * Normally this would be accomplished by clocking the line until SCL and SDA
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+ * are released and then sending a start condtiion (From an Atmel datasheet).
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+ * There is no direct access to the i2c pins so instead create start commands
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+ * through the i2c interface. Send a start command then delay for the SDA Hold
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+ * time, repeat this by disabling/enabling the bus a total of 9 times.
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+ */
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+static void send_reset(void)
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+{
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+ struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
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+ int i;
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+ u32 delay;
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+ u8 fdr;
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+ int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
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+ struct mpc5xxx_i2c_tap scltap[] = {
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+ {4, 1},
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+ {4, 2},
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+ {6, 4},
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+ {6, 8},
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+ {14, 16},
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+ {30, 32},
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+ {62, 64},
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+ {126, 128}
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+ };
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+
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+ fdr = (u8)mpc_reg_in(®s->mfdr);
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+
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+ delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
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+ scltap[FDR432(fdr)].tap2tap) + 3;
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+
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+ for (i = 0; i < 9; i++) {
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+ mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
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+ udelay(delay);
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+ mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK);
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+ udelay(delay);
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+ }
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+
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+ mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
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+}
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+#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
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+
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/**************** I2C API ****************/
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void i2c_init(int speed, int saddr)
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@@ -225,6 +271,9 @@ void i2c_init(int speed, int saddr)
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mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
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mpc_reg_out(®s->msr, 0, I2C_IF);
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+#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
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+ send_reset();
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+#endif
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return;
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}
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