* Patch by Dave Ellis, 22 May 2003:

  Fix problem with only partially cleared .bss segment

* Patch by Rune Torgersen, 12 May 2003:
  get PCI to work on a MPC8266ADS board; incorporate change to
  cpu/mpc8260/pci.c to enable overrides of PCI memory parameters

CHANGELOG

@@ -2,6 +2,19 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patch by Dave Ellis, 22 May 2003:
+  Fix problem with only partially cleared .bss segment
+
+* Patch by Rune Torgersen, 12 May 2003:
+  get PCI to work on a MPC8266ADS board; incorporate change to
+  cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
+
+* Patch by Nye Liu, 1 May 2003:
+  minor patches for the FADS8xx
+
+* Patch by Thomas Schäfer, 28 Apr 2003:
+  Fix SPD handling for 256 ECC DIMM on Walnut
+
 * Add support for arbitrary bitmaps for TRAB's  VFD command;
   allow to pass boot bitmap addresses in environment variables;
   allow for zero boot delay

README

@@ -1710,6 +1710,16 @@ Low Level (hardware related) configuration options:
 		#define'd default value in commproc.h resp.
 		cpm_8260.h.
 
+- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB, 
+  CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL, 
+  CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS, 
+  CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB, 
+  CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, 
+  CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL, 
+  CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE, 
+  CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
+		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+
 Building the Software:
 ======================
 

board/cray/L1/Makefile

@@ -25,21 +25,21 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	= $(BOARD).o flash.o bootscript.o
+OBJS	= $(BOARD).o flash.o
 SOBJS	= init.o 
 
-$(LIB):	$(OBJS) $(SOBJS)
+# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
+# built in the depend stage.  So... put bootscript.o here, not in OBJS
+$(LIB):	$(OBJS) $(SOBJS) bootscript.o
 	$(AR) crv $@ $^
 
 clean:
-	rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image
+	rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o
 
 distclean:	clean
 	rm -f $(LIB) core *.bak .depend
 
-$(BOARD).o: $(BOARD).c bootscript.o
-
-bootscript.o: bootscript.c
+$(BOARD).o : $(BOARD).c bootscript.o
 
 bootscript.c: bootscript.image
 	od -t x1 -v -A x $^ | awk -f x2c.awk > $@

board/fads/fads.c

@@ -208,6 +208,7 @@ int checkboard (void)
 	case 0x22 :
 	case 0x23 :
 	case 0x24 :
+	case 0x2a :
 	case 0x3f :
 		puts ("FADS");
 		break;

board/fads/flash.c

@@ -147,7 +147,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 	int i;
 
 	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080 ) {
 		/* set sector offsets for uniform sector type	*/
 		for (i = 0; i < info->sector_count; i++) {
 			info->start[i] = base + (i * 0x00040000);
@@ -179,6 +179,8 @@ void flash_print_info  (flash_info_t *info)
 	{
 		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
 			break;
+		case FLASH_AM080:	printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
+		                	break;
 		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
 					break;
 		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
@@ -278,6 +280,12 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			info->size = 0x00200000;
 			break;				/* => 2 MB		*/
 
+		case AMD_ID_F080B:
+			info->flash_id += FLASH_AM080;
+			info->sector_count =16;
+			info->size = 0x00400000;
+			break;				/* => 4 MB		*/
+
 		case AMD_ID_LV400T:
 			info->flash_id += FLASH_AM400T;
 			info->sector_count = 11;

board/mpc8266ads/config.mk

@@ -27,6 +27,6 @@
 # mpc8260ads board
 #
 
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xfe000000
 
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/mpc8266ads/flash.c

@@ -55,7 +55,7 @@ static int clear_block_lock_bit(vu_long * addr);
 
 unsigned long flash_init (void)
 {
-#ifndef CONFIG_MPC8260ADS
+#ifndef CONFIG_MPC8266ADS
 	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
 	volatile memctl8xx_t	*memctl = &immap->im_memctl;
 	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
@@ -66,7 +66,7 @@ unsigned long flash_init (void)
 	/* Init: enable write,
 	 * or we cannot even write flash commands
 	 */
-#ifndef CONFIG_MPC8260ADS
+#ifndef CONFIG_MPC8266ADS
 	bcsr->bd_ctrl |= BD_CTRL_FLWE;
 #endif
 
@@ -86,7 +86,7 @@ unsigned long flash_init (void)
 			size, size<<20);
 	}
 
-#ifndef CONFIG_MPC8260ADS
+#ifndef CONFIG_MPC8266ADS
 	/* Remap FLASH according to real size */
 	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
 	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |

board/mpc8266ads/mpc8266ads.c

@@ -32,6 +32,7 @@
 #include <ioports.h>
 #include <i2c.h>
 #include <mpc8260.h>
+#include <pci.h>
 
 /*
  * PBI Page Based Interleaving
@@ -155,8 +156,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDC */
-	/* PC9  */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT970 FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
 	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
@@ -216,6 +217,11 @@ typedef struct bscr_ {
 	unsigned long bcsr7;
 } bcsr_t;
 
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+} pci_ic_t;
+
 void reset_phy(void)
 {
     volatile bcsr_t  *bcsr           = (bcsr_t *)CFG_BCSR;
@@ -229,8 +235,13 @@ void reset_phy(void)
 int board_pre_init (void)
 {
     volatile bcsr_t  *bcsr         = (bcsr_t *)CFG_BCSR;
-    bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1;
+    volatile pci_ic_t *pci_ic      = (pci_ic_t *) CFG_PCI_INT;
+
+    bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
 
+    /* mask all PCI interrupts */
+    pci_ic->pci_int_mask |= 0xfff00000;
+    
     return 0;
 }
 
@@ -250,7 +261,7 @@ long int initdram(int board_type)
     uint  psdmr = CFG_PSDMR;
     int i;
 
-    uint   psrt = 14;					/* for no SPD */
+    uint   psrt = 0x21;					/* for no SPD */
     uint   chipselects = 1;				/* for no SPD */
     uint   sdram_size = CFG_SDRAM_SIZE * 1024 * 1024;	/* for no SPD */
     uint   or = CFG_OR2_PRELIM;				/* for no SPD */
@@ -270,7 +281,7 @@ long int initdram(int board_type)
     int    j;
 
     /* Keep the compiler from complaining about potentially uninitialized vars */
-    data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
+    data_width = rows = banks = cols = caslatency = 0;
 
     /*
      * Read the SDRAM SPD EEPROM via I2C.
@@ -294,17 +305,18 @@ long int initdram(int board_type)
 		{
 			/*
 				 * Refresh rate: this assumes the prescaler is set to
-			 * approximately 1uSec per tick.
+			 * approximately 0.39uSec per tick and the target refresh period 
+			 * is about 85% of maximum.
 			 */
 			switch(data & 0x7F) 
 			{
 					default:
-					case 0:  psrt =  16; /*  15.625uS */  break;
-					case 1:  psrt =   2;  /*   3.9uS   */  break;
-					case 2:  psrt =   6;  /*   7.8uS   */  break;
-					case 3:  psrt =  29;  /*  31.3uS   */  break;
-					case 4:  psrt =  60;  /*  62.5uS   */  break;
-					case 5:  psrt = 120;  /* 125uS     */  break;
+					case 0:  psrt = 0x21; /*  15.625uS */  break;
+					case 1:  psrt = 0x07; /*   3.9uS   */  break;
+					case 2:  psrt = 0x0F; /*   7.8uS   */  break;
+					case 3:  psrt = 0x43; /*  31.3uS   */  break;
+					case 4:  psrt = 0x87; /*  62.5uS   */  break;
+					case 5:  psrt = 0xFF; /* 125uS     */  break;
 			}
 		}
 		else if(j == 17) banks       = data;
@@ -563,3 +575,14 @@ long int initdram(int board_type)
     return (sdram_size * chipselects);
 	/*return (16 * 1024 * 1024);*/
 }
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

common/cmd_pci.c

@@ -113,7 +113,7 @@ void pciinfo(int BusNum, int ShortPCIListing)
     }
 }
 
-char* pci_classes_str(u8 class)
+static char *pci_classes_str(u8 class)
 {
 	switch (class) {
         case PCI_CLASS_NOT_DEFINED:
@@ -123,55 +123,55 @@ char* pci_classes_str(u8 class)
                 return "Mass storage controller";
                 break;
         case PCI_BASE_CLASS_NETWORK:
-                return "Network controller     ";
+                return "Network controller";
                 break;
         case PCI_BASE_CLASS_DISPLAY:
-                return "Display controller     ";
+                return "Display controller";
                 break;
         case PCI_BASE_CLASS_MULTIMEDIA:
-                return "Multimedia device      ";
+                return "Multimedia device";
                 break;
         case PCI_BASE_CLASS_MEMORY:
-                return "Memory controller      ";
+                return "Memory controller";
                 break;
         case PCI_BASE_CLASS_BRIDGE:
-                return "Bridge device          ";
+                return "Bridge device";
                 break;
         case PCI_BASE_CLASS_COMMUNICATION:
                 return "Simple comm. controller";
                 break;
         case PCI_BASE_CLASS_SYSTEM:
-                return "Base system peripheral ";
+                return "Base system peripheral";
                 break;
         case PCI_BASE_CLASS_INPUT:
-                return "Input device           ";
+                return "Input device";
                 break;
         case PCI_BASE_CLASS_DOCKING:
-                return "Docking station        ";
+                return "Docking station";
                 break;
         case PCI_BASE_CLASS_PROCESSOR:
-                return "Processor              ";
+                return "Processor";
                 break;
         case PCI_BASE_CLASS_SERIAL:
-                return "Serial bus controller  ";
+                return "Serial bus controller";
                 break;
         case PCI_BASE_CLASS_INTELLIGENT:
-                return "Intelligent controller ";
+                return "Intelligent controller";
                 break;
         case PCI_BASE_CLASS_SATELLITE:
-                return "Satellite controller   ";
+                return "Satellite controller";
                 break;
         case PCI_BASE_CLASS_CRYPT:
-                return "Cryptographic device   ";
+                return "Cryptographic device";
                 break;
         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
-                return "DSP                    ";
+                return "DSP";
                 break;
         case PCI_CLASS_OTHERS:
-                return "Does not fit any class ";
+                return "Does not fit any class";
                 break;
         default:
-	return  "???                    ";
+	return  "???";
                 break;
 	};
 }
@@ -197,7 +197,7 @@ void pci_header_show_brief(pci_dev_t dev)
 	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
 	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
 
-	printf("0x%.4x     0x%.4x     %s 0x%.2x\n",
+	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
 	       vendor, device,
 	       pci_classes_str(class), subclass);
 }

cpu/74xx_7xx/start.S

@@ -69,7 +69,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 	END_GOT
 
 /*
@@ -716,7 +716,7 @@ in_ram:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 	lwz	r4,GOT(_end)
 
 	cmplw	0, r3, r4

cpu/mpc5xx/start.S

@@ -67,7 +67,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 	END_GOT
 
 /*
@@ -527,7 +527,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 	lwz	r4,GOT(_end)
 	cmplw	0, r3, r4
 	beq	6f

cpu/mpc824x/start.S

@@ -74,7 +74,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 #if defined(CONFIG_FADS)
 	GOT_ENTRY(environment)
 #endif
@@ -665,7 +665,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 	lwz	r4,GOT(_end)
 
 	cmplw	0, r3, r4

cpu/mpc8260/pci.c

@@ -26,22 +26,30 @@
 #ifdef CONFIG_PCI
 
 #include <pci.h>
+#include <mpc8260.h>
 #include <asm/m8260_pci.h>
 
 /*
  *   Local->PCI map (from CPU)                             controlled by
  *   MPC826x master window
  *
- *   0x80000000 - 0xBFFFFFFF    Total CPU2PCI space        PCIBR0
+ *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
+ *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
  *                       
- *   0x80000000 - 0x8FFFFFFF    PCI Mem with prefetch      (Outbound ATU #1)
- *   0x90000000 - 0x9FFFFFFF    PCI Mem w/o  prefetch      (Outbound ATU #2)
- *   0xA0000000 - 0xAFFFFFFF    32-bit PCI IO              (Outbound ATU #3)
+ *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
+ *                              PCI Mem with prefetch
+ *
+ *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
+ *                              PCI Mem w/o  prefetch
+ *
+ *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
+ *                              32-bit PCI IO
  *                      
  *   PCI->Local map (from PCI)
  *   MPC826x slave window                                  controlled by
  *
- *   0x00000000 - 0x07FFFFFF    MPC826x local memory       (Inbound ATU #1)
+ *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
+ *                              MPC826x local memory
  */
 
 /* 
@@ -49,20 +57,57 @@
  * This window is set up using the first set of Inbound ATU registers
  */
 
-#define PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#ifndef CFG_PCI_SLV_MEM_LOCAL 
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */ 
+#else 
+#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL 
+#endif
+
+#ifndef CFG_PCI_SLV_MEM_BUS
+#define PCI_SLV_MEM_BUS 0x00000000		/* PCI base */
+#else
+#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
+#endif
+
+#ifndef CFG_PICMR0_MASK_ATTRIB
 #define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
                           	 PICMR_PREFETCH_EN)
+#else
+#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
+#endif
 
 /* 
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window. 
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI 
+ * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * these windows.
  */
 
-#define PCI_MSTR_LOCAL		0x80000000		/* Local base */
+/* PCIBR0 */
+#ifndef CFG_PCI_MSTR0_LOCAL
+#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */ 
+#else 
+#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
+#endif
+
+#ifndef CFG_PCIMSK0_MASK
 #define PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+#else
+#define PCIMSK0_MASK	CFG_PCIMSK0_MASK
+#endif
+
+/* PCIBR1 */
+#ifndef CFG_PCI_MSTR1_LOCAL
+#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */ 
+#else 
+#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL 
+#endif
+
+#ifndef CFG_PCIMSK1_MASK
+#define  PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+#else
+#define  PCIMSK1_MASK		CFG_PCIMSK1_MASK
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI Memory (prefetch).
@@ -70,11 +115,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define PCI_MSTR_MEM_SIZE	0x10000000          /* 256MB */
+#ifndef CFG_PCI_MSTR_MEM_LOCAL
+#define PCI_MSTR_MEM_LOCAL 0x80000000          /* Local base */
+#else
+#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#endif
+
+#ifndef CFG_PCI_MSTR_MEM_BUS
+#define PCI_MSTR_MEM_BUS 0x80000000          /* PCI base   */
+#else
+#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
+#endif
+
+#ifndef CFG_CPU_PCI_MEM_START
+#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#else
+#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
+#endif
+
+#ifndef CFG_PCI_MSTR_MEM_SIZE
+#define PCI_MSTR_MEM_SIZE 0x10000000          /* 256MB */
+#else
+#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
+#endif
+
+#ifndef CFG_POCMR0_MASK_ATTRIB
 #define POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#else
+#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -82,11 +151,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_MEMIO_LOCAL    0x90000000          /* Local base */
-#define PCI_MSTR_MEMIO_BUS      0x90000000          /* PCI base   */
-#define CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define PCI_MSTR_MEMIO_SIZE     0x10000000          /* 256MB */
-#define POCMR1_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE)
+#ifndef CFG_PCI_MSTR_MEMIO_LOCAL 
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */ 
+#else 
+#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL 
+#endif
+
+#ifndef CFG_PCI_MSTR_MEMIO_BUS 
+#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */ 
+#else 
+#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS 
+#endif
+
+#ifndef CFG_CPU_PCI_MEMIO_START 
+#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 
+#else 
+#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START 
+#endif
+
+#ifndef CFG_PCI_MSTR_MEMIO_SIZE 
+#define PCI_MSTR_MEMIO_SIZE 0x20000000          /* 512MB */ 
+#else 
+#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE 
+#endif
+
+#ifndef CFG_POCMR1_MASK_ATTRIB
+#define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#else
+#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI IO space.
@@ -94,15 +187,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_IO_LOCAL       0xA0000000          /* Local base */
-#ifdef CONFIG_ATC
-#define PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#else
-#define PCI_MSTR_IO_BUS         0xA0000000          /* PCI base   */
+#ifndef CFG_PCI_MSTR_IO_LOCAL 
+#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */ 
+#else 
+#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL 
+#endif
+
+#ifndef CFG_PCI_MSTR_IO_BUS 
+#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */ 
+#else 
+#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS 
+#endif
+
+#ifndef CFG_CPU_PCI_IO_START 
+#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 
+#else 
+#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START 
+#endif
+
+#ifndef CFG_PCI_MSTR_IO_SIZE 
+#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */ 
+#else 
+#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE 
 #endif
-#define CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define PCI_MSTR_IO_SIZE        0x10000000          /* 256MB */
+
+#ifndef CFG_POCMR2_MASK_ATTRIB
 #define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
+#else
+#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
+#endif
 
 /* PCI bus configuration registers.
  */
@@ -117,6 +230,9 @@ static inline void  pci_outl(u32 addr, u32 data)
 
 void pci_mpc8250_init(struct pci_controller *hose)
 {
+#ifdef CONFIG_MPC8266ADS
+    DECLARE_GLOBAL_DATA_PTR;
+#endif
     u16 tempShort;
     u32 immr_addr = CFG_IMMR;
     volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -125,11 +241,19 @@ void pci_mpc8250_init(struct pci_controller *hose)
     pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
 	                         CFG_IMMR + PCI_CFG_DATA_REG);
 
+    /*
+     * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
+     */
+#ifdef CONFIG_MPC8266ADS
+    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+				   | SIUMCR_LBPC01;
+#else
     /* 
      * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
      * and local bus for PCI (SIUMCR [LBPC]).
      */
     immap->im_siu_conf.sc_siumcr = 0x00640000;
+#endif
 
     /* Make PCI lowest priority */
     /* Each 4 bits is a device bus request  and the MS 4bits 
@@ -153,18 +277,33 @@ void pci_mpc8250_init(struct pci_controller *hose)
     immap->im_siu_conf.sc_ppc_acr = 0x6;
 
     /* 
-     * Set up master window that allows the CPU to access PCI space. This 
-     * window is set up using the first SIU PCIBR registers.
+     * Set up master windows that allow the CPU to access PCI space. These 
+     * windows are set up using the two SIU PCIBR registers.
      */
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
     *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
-	    PCI_MSTR_LOCAL | PCIBR_ENABLE;
+	    PCI_MSTR0_LOCAL | PCIBR_ENABLE;
+
+#ifdef CONFIG_MPC8266ADS
+    *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
+    *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
+	    PCI_MSTR1_LOCAL | PCIBR_ENABLE;
+#endif 
 
     /* Release PCI RST (by default the PCI RST signal is held low)  */
     pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
 
     /* give it some time */
-    udelay(1000);
+    {
+#ifdef CONFIG_MPC8266ADS 
+		/* Give the PCI cards more time to initialize before query 
+			This might be good for other boards also
+		*/
+        int i;
+        for (i = 0; i < 1000; ++i)
+#endif
+            udelay(1000);
+    }
 
     /* 
      * Set up master window that allows the CPU to access PCI Memory (prefetch) 
@@ -218,18 +357,34 @@ void pci_mpc8250_init(struct pci_controller *hose)
     hose->last_busno = 0xff;
 
     /* System memory space */
+#ifdef CONFIG_MPC8266ADS
+    pci_set_region(hose->regions + 0,
+		       PCI_SLV_MEM_BUS,
+		       PCI_SLV_MEM_LOCAL,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#else
     pci_set_region(hose->regions + 0,
 		       CFG_SDRAM_BASE,
 		       CFG_SDRAM_BASE,
 		       0x4000000,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#endif
 
     /* PCI memory space */
+#ifdef CONFIG_MPC8266ADS
+    pci_set_region(hose->regions + 0,
+		       PCI_SLV_MEM_BUS,
+		       PCI_SLV_MEM_LOCAL,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#else
     pci_set_region(hose->regions + 1,
 		       PCI_MSTR_MEM_BUS,
 		       PCI_MSTR_MEM_LOCAL,
 		       PCI_MSTR_MEM_SIZE,
 		       PCI_REGION_MEM);
+#endif
 
     /* PCI I/O space */
     pci_set_region(hose->regions + 2,

cpu/mpc8260/start.S

@@ -67,7 +67,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 #if defined(CONFIG_HYMOD)
 	GOT_ENTRY(environment)
 #endif
@@ -987,7 +987,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 #if defined(CONFIG_HYMOD)
 	/*
 	 * For HYMOD - the environment is the very last item in flash.

cpu/mpc8xx/start.S

@@ -74,7 +74,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 #if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
 	GOT_ENTRY(environment)
 #endif
@@ -684,7 +684,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 #if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
 	/*
 	 * For the FADS - the environment is the very last item in flash.

cpu/ppc4xx/spd_sdram.c

@@ -289,7 +289,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 	/* now check for ECC ability of module. We only support ECC
 	 *   on 32 bit wide devices with 8 bit ECC.
 	 */
-	if ( (read_spd(11)==2) && ((read_spd(6)==40) || (read_spd(14)==8)) ){
+	if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
 	   sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 	   ecc_on = 1;
    	}

cpu/ppc4xx/start.S

@@ -133,7 +133,7 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(_end)
-	GOT_ENTRY(.bss)
+	GOT_ENTRY(__bss_start)
 	END_GOT
 
 /*
@@ -1339,7 +1339,7 @@ clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
-	lwz	r3,GOT(.bss)
+	lwz	r3,GOT(__bss_start)
 	lwz	r4,GOT(_end)
 
 	cmplw	0, r3, r4

drivers/pci_indirect.c

@@ -21,7 +21,7 @@
 #define cfg_read(val, addr, type, op)	*val = op((type)(addr))
 #define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
 
-#if defined(CONFIG_PM826) || defined(CONFIG_ATC)
+#if defined(CONFIG_MPC8260)
 #define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
 static int								 \
 indirect_##rw##_config_##size(struct pci_controller *hose, 		 \

include/configs/FADS860T.h

@@ -159,8 +159,8 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/

include/configs/MPC8260ADS.h

@@ -191,7 +191,7 @@
 /* this is stuff came out of the Motorola docs */
 #define CFG_DEFAULT_IMMR	0x0F010000
 
-#define CFG_IMMR		0x04700000
+#define CFG_IMMR		0xF0000000
 #define CFG_BCSR		0x04500000
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_LSDRAM_BASE		0x04000000

include/configs/MPC8266ADS.h

@@ -39,7 +39,7 @@
  */
 
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
-#define CONFIG_MPC8260ADS	1	/* ...on motorola ads board */
+#define CONFIG_MPC8266ADS	1	/* ...on motorola ads board */
 
 #define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
 
@@ -78,6 +78,23 @@
 #define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
 #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
 
 #if (CONFIG_ETHER_INDEX == 2)
 
@@ -90,7 +107,7 @@
 # define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 # define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 # define CFG_CPMFCR_RAMTYPE	0
-# define CFG_FCC_PSMR		0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #endif	/* CONFIG_ETHER_INDEX */
 
@@ -100,6 +117,12 @@
 #define CFG_I2C_SLAVE		0x7F
 #define CFG_I2C_EEPROM_ADDR_LEN 1
 
+/* PCI */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#undef CONFIG_PCI_SCAN_SHOW
+
 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
  * (to get SDRAM settings)
@@ -107,7 +130,7 @@
 #define SPD_EEPROM_ADDRESS      0x50
 
 
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
 #define CONFIG_BAUDRATE		115200
 
 
@@ -116,6 +139,7 @@
 				 CFG_CMD_BMP	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
+				 CFG_CMD_DHCP   | \
 				 CFG_CMD_DOC	| \
 				 CFG_CMD_DTT	| \
 				 CFG_CMD_EEPROM | \
@@ -127,21 +151,51 @@
 				 CFG_CMD_JFFS2	| \
 				 CFG_CMD_KGDB	| \
 				 CFG_CMD_NAND	| \
-				 CFG_CMD_MII	| \
-				 CFG_CMD_PCI	| \
 				 CFG_CMD_PCMCIA | \
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
 				 CFG_CMD_VFD	| \
 				 CFG_CMD_USB	) )
 
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#define CONFIG_BOOT_ROOT_INITRD 0	/* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS	1	/* Use a NFS mounted root file system */
+
+#if CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#if CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS)
+
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
 
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
@@ -170,7 +224,7 @@
 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
 					/* for versions < 2.4.5-pre5	*/
 
 #define CFG_LOAD_ADDR		0x100000	/* default load address */
@@ -179,8 +233,8 @@
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#define CFG_FLASH_BASE		0xff800000
-#define FLASH_BASE		0xff800000
+#define CFG_FLASH_BASE		0xFE000000
+#define FLASH_BASE		0xFE000000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
 #define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
 #define CFG_FLASH_SIZE		8
@@ -193,14 +247,10 @@
 /* Only change this if you also change the Hardware configuration Word */
 #define CFG_DEFAULT_IMMR	0x0F010000
 
-/*
-#define CFG_IMMR		0x04700000
-#define CFG_BCSR		0x04500000
-*/
-
 /* Set IMMR to 0xF0000000 or above to boot Linux  */
 #define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0x04500000
+#define CFG_BCSR		0xF8000000
+#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
 
 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
  */
@@ -263,7 +313,7 @@
 			 ORxS_ROWST_PBI0_A8		|\
 			 ORxS_NUMR_12)
 #elif (CFG_SDRAM_SIZE == 16)
-#define CFG_OR2_PRELIM	(0xFF000CA0)
+#define CFG_OR2_PRELIM	(0xFF000C80)
 #else
 #error "INVALID SDRAM CONFIGURATION"
 #endif
@@ -325,13 +375,13 @@
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 
 
-/* 0x0EA28205 */
-/*#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
-			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
-			    ( HRCW_BMS | HRCW_APPC10 )			    |\
-			    ( HRCW_MODCK_H0101 )			     \
+/* 0x0EB2B645 */
+#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
+			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
+			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
+			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
 			)
-*/
+
 
 /* This value should actually be situated in the first 256 bytes of the FLASH
 	which on the standard MPC8266ADS board is at address 0xFF800000
@@ -346,7 +396,7 @@
 	- Rune
 
 	*/
-#define CFG_HRCW_MASTER 0x0cb23645
+/* #define CFG_HRCW_MASTER 0x0cb23645 */
 
 /* no slaves */
 #define CFG_HRCW_SLAVE1 0
@@ -392,22 +442,98 @@
 #define CFG_HID2		0
 
 #define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x100C0000
-#define CFG_SIUMCR		0x0A200000
+#define CFG_BCR			0x004C0000
+#define CFG_SIUMCR		0x4E64C000
 #define CFG_SCCR		0x00000000
-#define CFG_BR0_PRELIM		0xFF801801
-#define CFG_OR0_PRELIM		0xFF800836
-#define CFG_BR1_PRELIM		0x04501801
-#define CFG_OR1_PRELIM		0xFFFF8010
 
-#define CFG_RMR			0
+/*	local bus memory map
+ *
+ *	0x00000000-0x03FFFFFF	 64MB	SDRAM
+ *	0x80000000-0x9FFFFFFF	512MB	outbound prefetchable PCI memory window
+ *	0xA0000000-0xBFFFFFFF	512MB	outbound non-prefetchable PCI memory window
+ *	0xF0000000-0xF001FFFF	128KB	MPC8266 internal memory
+ *	0xF4000000-0xF7FFFFFF	 64MB   outbound PCI I/O window
+ *	0xF8000000-0xF8007FFF	 32KB	BCSR
+ *	0xF8100000-0xF8107FFF	 32KB	ATM UNI
+ *	0xF8200000-0xF8207FFF	 32KB	PCI interrupt controller
+ *	0xF8300000-0xF8307FFF	 32KB	EEPROM
+ *	0xFE000000-0xFFFFFFFF	 32MB	flash
+ */
+#define CFG_BR0_PRELIM	0xFE001801		/* flash */
+#define CFG_OR0_PRELIM	0xFE000836
+#define CFG_BR1_PRELIM	(CFG_BCSR | 0x1801)	/* BCSR */
+#define CFG_OR1_PRELIM	0xFFFF8010
+#define CFG_BR4_PRELIM	0xF8300801		/* EEPROM */
+#define CFG_OR4_PRELIM	0xFFFF8846
+#define CFG_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
+#define CFG_OR5_PRELIM	0xFFFF8E36
+#define CFG_BR8_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CFG_OR8_PRELIM	0xFFFF8010
+
+#define CFG_RMR			0x0001
 #define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 #define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
 #define CFG_RCCR		0
-/*#define CFG_PSDMR		0x016EB452*/
 #define CFG_MPTPR		0x00001900
 #define CFG_PSRT		0x00000021
 
 #define CFG_RESET_ADDRESS	0x04400000
 
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+                          	 PICMR_PREFETCH_EN)
+
+/* 
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI 
+ * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * these windows.
+ */
+
+/* PCIBR0 */
+#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+/* PCIBR1 */
+#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+
+/* 
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/* 
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/* 
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the third set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF4000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x04000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
 #endif /* __CONFIG_H */

include/configs/PM826.h

@@ -155,12 +155,22 @@
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_BEDBUG	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_PCI)
+#else	/* ! PCI */
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
 				 CFG_CMD_BEDBUG	| \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_DOC	| \
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_I2C	)
+#endif	/* CONFIG_PCI */
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

include/configs/WALNUT405.h

@@ -191,7 +191,7 @@
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFFF80000
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 
 /*

include/configs/atc.h

@@ -248,6 +248,7 @@
 
 #define	CONFIG_PCI
 #define	CONFIG_PCI_PNP
+#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
 
 #if 1
 /* environment is in Flash */

include/flash.h

@@ -129,6 +129,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 					/* 4 Mbit, 512K x 8,			*/
 					/* 8 64K x 8 uniform sectors		*/
 #define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
+					/* 8 Mbit, 512K x 16,			*/
+					/* 8 64K x 16 uniform sectors		*/
 #define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
 #define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
 #define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
@@ -219,13 +221,12 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
  * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
  */
 
-#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B
-					 * Bright Micro BM29F040
-					 * Fujitsu MBM29F040A
-					 * STM M29W040B
-					 * SGS Thomson M29F040B
-					 * 8 64K x 8 uniform sectors
-					 */
+#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B            */
+					/* Bright Micro BM29F040                */
+					/* Fujitsu MBM29F040A                   */
+					/* STM M29W040B                         */
+					/* SGS Thomson M29F040B                 */
+					/* 8 64K x 8 uniform sectors            */
 #define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
 #define FLASH_AM400B	0x0003
 #define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
@@ -237,6 +238,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
 #define FLASH_AM320B	0x0009
 
+#define FLASH_AM080	0x000A		/* AMD Am29F080B                        */
+					/* 16 64K x 8 uniform sectors           */
+
 #define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
 #define FLASH_AMDL322B	0x0011
 #define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/

lib_ppc/board.c

@@ -843,6 +843,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
     defined(CONFIG_IVMS8)	|| \
     defined(CONFIG_LWMON)	|| \
     defined(CONFIG_MPC8260ADS)	|| \
+    defined(CONFIG_MPC8266ADS)	|| \
     defined(CONFIG_PCU_E)	|| \
     defined(CONFIG_RPXSUPER)	|| \
     defined(CONFIG_SPD823TS)	)