corenet_ds: pick the middle value for all tested timing parameters

For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>

board/freescale/corenet_ds/ddr.c

@@ -170,27 +170,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = {
 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
 	 * mhz| mhz|ranks|adjst| start | delay|
 	 */
-		{  0, 333,    4,    5,     7,   0xff,    2,  0},
-		{334, 400,    4,    5,     7,   0xff,    2,  0},
-		{401, 549,    4,    5,     7,   0xff,    2,  0},
-		{550, 680,    4,    5,     7,   0xff,    2,  0},
-		{681, 850,    4,    5,     7,   0xff,    2,  0},
-		{851, 1050,   4,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
-		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
-		{  0, 333,    2,    5,     7,   0xff,    2,  0},
-		{334, 400,    2,    5,     7,   0xff,    2,  0},
-		{401, 549,    2,    5,     7,   0xff,    2,  0},
-		{550, 680,    2,    5,     7,   0xff,    2,  0},
-		{681, 850,    2,    5,     7,   0xff,    2,  0},
-		{851, 1050,   2,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{  0, 850,    4,    1,     5,   0xff,    2,  0},
+		{851, 950,    4,    3,     5,   0xff,    2,  0},
+		{951, 1050,   4,    5,     8,   0xff,    2,  0},
+		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
+		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{  0, 850,    2,    5,     6,   0xff,    2,  0},
+		{851, 950,    2,    5,     7,   0xff,    2,  0},
+		{951, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
-		{  0, 333,    1,    5,     7,   0xff,    2,  0},
-		{334, 400,    1,    5,     7,   0xff,    2,  0},
-		{401, 549,    1,    5,     7,   0xff,    2,  0},
-		{550, 680,    1,    5,     7,   0xff,    2,  0},
-		{681, 850,    1,    5,     7,   0xff,    2,  0}
 	},
 
 	{
@@ -199,27 +188,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = {
 	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
 	 * mhz| mhz|ranks|adjst| start | delay|
 	 */
-		{  0, 333,    4,    5,     7,   0xff,    2,  0},
-		{334, 400,    4,    5,     7,   0xff,    2,  0},
-		{401, 549,    4,    5,     7,   0xff,    2,  0},
-		{550, 680,    4,    5,     7,   0xff,    2,  0},
-		{681, 850,    4,    5,     7,   0xff,    2,  0},
-		{851, 1050,   4,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
-		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
-		{  0, 333,    2,    5,     7,   0xff,    2,  0},
-		{334, 400,    2,    5,     7,   0xff,    2,  0},
-		{401, 549,    2,    5,     7,   0xff,    2,  0},
-		{550, 680,    2,    5,     7,   0xff,    2,  0},
-		{681, 850,    2,    5,     7,   0xff,    2,  0},
-		{851, 1050,   2,    5,     7,   0xff,    2,  0},
-		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{  0, 850,    4,    1,     5,   0xff,    2,  0},
+		{851, 950,    4,    3,     5,   0xff,    2,  0},
+		{951, 1050,   4,    5,     8,   0xff,    2,  0},
+		{1051, 1250,  4,    5,    10,   0xff,    2,  0},
+		{1251, 1350,  4,    5,    11,   0xff,    2,  0},
+		{  0, 850,    2,    5,     6,   0xff,    2,  0},
+		{851, 950,    2,    5,     7,   0xff,    2,  0},
+		{951, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    4,     6,   0xff,    2,  0},
 		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
-		{  0, 333,    1,    5,     7,   0xff,    2,  0},
-		{334, 400,    1,    5,     7,   0xff,    2,  0},
-		{401, 549,    1,    5,     7,   0xff,    2,  0},
-		{550, 680,    1,    5,     7,   0xff,    2,  0},
-		{681, 850,    1,    5,     7,   0xff,    2,  0}
 	}
 };