vf610: adding support for errata and no errata

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -237,11 +237,19 @@ struct anadig_reg {
 
 #define FASE_CLK_FREQ		24000000
 #define SLOW_CLK_FREQ		32000
+#ifdef VF610_500MHZ_ERRATA
+#define PLL1_PFD1_FREQ		474000000
+#define PLL1_PFD2_FREQ		428000000
+#define PLL1_PFD3_FREQ		375000000
+#define PLL1_PFD4_FREQ		500000000
+#define PLL1_MAIN_FREQ		500000000
+#else
 #define PLL1_PFD1_FREQ		500000000
 #define PLL1_PFD2_FREQ		452000000
 #define PLL1_PFD3_FREQ		396000000
 #define PLL1_PFD4_FREQ		528000000
 #define PLL1_MAIN_FREQ		528000000
+#endif
 #define PLL2_PFD1_FREQ		500000000
 #define PLL2_PFD2_FREQ		396000000
 #define PLL2_PFD3_FREQ		339000000

board/freescale/vf610twr/vf610twr.c

@@ -351,9 +351,11 @@ static void clock_init(void)
 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 
-#ifdef VF610_500MHZ
-	anadig->pll1_num = 83;
-	anadig->pll1_denom = 100;
+#ifdef VF610_500MHZ_ERRATA
+	//anadig->pll1_num = 83;
+	//anadig->pll1_denom = 100;
+	writel(100, &anadig->pll1_denom);
+	writel(83, &anadig->pll1_num);
 #endif
 
 
@@ -377,11 +379,16 @@ static void clock_init(void)
 		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
                 CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
-
+#if (defined(VF610_500MHZ_ERRATA) || defined (VF610_500MHZ))
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+			ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE |
+			ANADIG_PLL2_CTRL_DIV_SELECT);
+#else
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
-		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
-#ifdef VF610_500MHZ
-	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+			ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+#endif
+#ifdef VF610_500MHZ_ERRATA
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN | ANADIG_PLL1_CTRL_DIV_SELECT,
 		ANADIG_PLL1_CTRL_ENABLE);
 #else
 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
@@ -390,7 +397,8 @@ static void clock_init(void)
 
 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
-#ifdef VF610_500MHZ
+
+#ifdef VF610_500MHZ_ERRATA
 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 		CCM_CCSR_PLL1_PFD_CLK_SEL(0) | CCM_CCSR_PLL2_PFD4_EN |
 		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
@@ -398,6 +406,14 @@ static void clock_init(void)
 		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(0) |
 		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+#elif defined VF610_500MHZ
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(1) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(0) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 #else
 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
@@ -407,6 +423,7 @@ static void clock_init(void)
 		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
 #endif
+
 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 		CCM_CACRR_ARM_CLK_DIV(0));

include/configs/vf610twr.h

@@ -97,6 +97,8 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
+#define VF610_500MHZ
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(256<<10)