vf610: Setting PLL1 to 500MHz and setting sys_clk to PLL1 main clock, ddr_clk to PLL2_PFD2

board/freescale/vf610twr/vf610twr.c

@@ -351,6 +351,12 @@ static void clock_init(void)
 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 
+#ifdef VF610_500MHZ
+	anadig->pll1_num = 83;
+	anadig->pll1_denom = 100;
+#endif
+
+
 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 		CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
@@ -374,11 +380,25 @@ static void clock_init(void)
 
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
 		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+#ifdef VF610_500MHZ
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE);
+#else
 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+#endif
 
 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+#ifdef VF610_500MHZ
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(0) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(0) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+#else
 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
 		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
@@ -386,6 +406,7 @@ static void clock_init(void)
 		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
 		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
 		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+#endif
 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 		CCM_CACRR_ARM_CLK_DIV(0));