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@@ -1923,6 +1923,7 @@ typedef struct ccsr_gur {
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#define MPC85xx_PMUXCR_SD_DATA 0x80000000
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#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
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#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
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+#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
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#define MPC85xx_PMUXCR_QE0 0x00008000
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#define MPC85xx_PMUXCR_QE1 0x00004000
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#define MPC85xx_PMUXCR_QE2 0x00002000
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@@ -1998,10 +1999,14 @@ typedef struct ccsr_gur {
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u32 ddrioovcr; /* DDR IO Override Control */
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u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
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u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
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- u8 res16[61648];
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+ u8 res16[52];
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+ u32 sdhcdcr; /* SDHC debug control register */
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+ u8 res17[61592];
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} ccsr_gur_t;
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#endif
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+#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
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+
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typedef struct serdes_corenet {
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struct {
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u32 rstctl; /* Reset Control Register */
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