powerpc/85xx: Add P1021 specific QE and UEC support

P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode.  QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.

Also added relevant QE support defines unique to P1021.

The P1021 QE is shared on P1012, P1016, and P1025.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc85xx/speed.c

@@ -28,6 +28,7 @@
 
 #include <common.h>
 #include <ppc_asm.tmpl>
+#include <linux/compiler.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -156,7 +157,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 	int i;
 #ifdef CONFIG_QE
-	u32 qe_ratio;
+	__maybe_unused u32 qe_ratio;
 #endif
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
@@ -184,10 +185,15 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
 #ifdef CONFIG_QE
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	sysInfo->freqQE =  sysInfo->freqSystemBus;
+#else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
+#endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;

arch/powerpc/include/asm/config_mpc85xx.h

@@ -115,6 +115,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P1013 is single core version of P1022 */
 #elif defined(CONFIG_P1013)
@@ -155,6 +158,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -185,6 +191,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
@@ -225,6 +234,9 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
 
 /* P2010 is single core version of P2020 */
 #elif defined(CONFIG_P2010)

arch/powerpc/include/asm/immap_85xx.h

@@ -1923,6 +1923,19 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
+#define MPC85xx_PMUXCR_QE0		0x00008000
+#define MPC85xx_PMUXCR_QE1		0x00004000
+#define MPC85xx_PMUXCR_QE2		0x00002000
+#define MPC85xx_PMUXCR_QE3		0x00001000
+#define MPC85xx_PMUXCR_QE4		0x00000800
+#define MPC85xx_PMUXCR_QE5		0x00000400
+#define MPC85xx_PMUXCR_QE6		0x00000200
+#define MPC85xx_PMUXCR_QE7		0x00000100
+#define MPC85xx_PMUXCR_QE8		0x00000080
+#define MPC85xx_PMUXCR_QE9		0x00000040
+#define MPC85xx_PMUXCR_QE10		0x00000020
+#define MPC85xx_PMUXCR_QE11		0x00000010
+#define MPC85xx_PMUXCR_QE12		0x00000008
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 	u8	res6[8];
 	u32	devdisr;	/* Device disable control */
@@ -1956,29 +1969,36 @@ typedef struct ccsr_gur {
 	u8	res9[12];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
-	u8	res10a[8];
+	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
-	u8	res10b[76];
+	u8	res11a[76];
 	par_io_t qe_par_io[7];
-	u8	res10c[1600];
+	u8	res11b[1600];
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+      defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	u8      res11a[12];
+	u32     iovselsr;
+	u8      res11b[60];
+	par_io_t qe_par_io[3];
+	u8      res11c[1496];
 #else
-	u8	res10b[1868];
+	u8	res11a[1868];
 #endif
 	u32	clkdvdr;	/* Clock Divide register */
-	u8	res10d[1532];
+	u8	res12[1532];
 	u32	clkocr;		/* Clock out select */
-	u8	res11[12];
+	u8	res13[12];
 	u32	ddrdllcr;	/* DDR DLL control */
-	u8	res12[12];
+	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
-	u8	res13[248];
+	u8	res15[248];
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
 	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
 	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
-	u8	res15[61648];
+	u8	res16[61648];
 } ccsr_gur_t;
 #endif
 

drivers/qe/uec.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
@@ -588,9 +588,27 @@ static void phy_change(struct eth_device *dev)
 {
 	uec_private_t	*uec = (uec_private_t *)dev->priv;
 
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 	/* Update the link, speed, duplex */
 	uec->mii_info->phyinfo->read_status(uec->mii_info);
 
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	/*
+	 * QE12 is muxed with LBCTL, it needs to be released for enabling
+	 * LBCTL signal for LBC usage.
+	 */
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 	/* Adjust the interface according to speed */
 	adjust_link(dev);
 }
@@ -1198,10 +1216,21 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 	uec_private_t		*uec;
 	int			err, i;
 	struct phy_info         *curphy;
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 
 	uec = (uec_private_t *)dev->priv;
 
 	if (uec->the_first_run == 0) {
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 		err = init_phy(dev);
 		if (err) {
 			printf("%s: Cannot initialize PHY, aborting.\n",
@@ -1228,6 +1257,12 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 			udelay(100000);
 		} while (1);
 
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+    defined(CONFIG_P1021) || defined(CONFIG_P1025)
+		/* QE12 needs to be released for enabling LBCTL signal*/
+		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 		if (err || i <= 0)
 			printf("warning: %s: timeout on PHY link\n", dev->name);