PXA: pxa-regs.h cleanup

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

arch/arm/cpu/pxa/cpu.c

@@ -30,10 +30,11 @@
  * CPU specific code
  */
 
-#include <common.h>
-#include <command.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 #include <asm/system.h>
+#include <command.h>
+#include <common.h>
 
 static void cache_flush(void);
 
@@ -71,17 +72,22 @@ void set_GPIO_mode(int gpio_mode)
 {
 	int gpio = gpio_mode & GPIO_MD_MASK_NR;
 	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
-	int gafr;
+	int val;
+
+	/* This below changes direction setting of GPIO "gpio" */
+	val = readl(GPDR(gpio));
 
 	if (gpio_mode & GPIO_MD_MASK_DIR)
-	{
-		GPDR(gpio) |= GPIO_bit(gpio);
-	}
+		val |= GPIO_bit(gpio);
 	else
-	{
-		GPDR(gpio) &= ~GPIO_bit(gpio);
-	}
-	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
-	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
+		val &= ~GPIO_bit(gpio);
+
+	writel(val, GPDR(gpio));
+
+	/* This below updates only AF of GPIO "gpio" */
+	val = readl(GAFR(gpio));
+	val &= ~(0x3 << (((gpio) & 0xf) * 2));
+	val |= fn << (((gpio) & 0xf) * 2);
+	writel(val, GAFR(gpio));
 }
 #endif /* CONFIG_CPU_MONAHANS */

arch/arm/cpu/pxa/i2c.c

@@ -33,6 +33,7 @@
 /* FIXME: this file is PXA255 specific! What about other XScales? */
 
 #include <common.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_HARD_I2C
 
@@ -93,19 +94,21 @@ struct i2c_msg {
 
 static void i2c_reset( void )
 {
-	ICR &= ~ICR_IUE;		/* disable unit */
-	ICR |= ICR_UR;			/* reset the unit */
+	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
+	writel(readl(ICR) | ICR_UR, ICR);	/* reset the unit */
 	udelay(100);
-	ICR &= ~ICR_IUE;		/* disable unit */
+	writel(readl(ICR) & ~ICR_IUE, ICR);	/* disable unit */
 #ifdef CONFIG_CPU_MONAHANS
-	CKENB |= (CKENB_4_I2C); /*  | CKENB_1_PWM1 | CKENB_0_PWM0); */
+	/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
 #else /* CONFIG_CPU_MONAHANS */
-	CKEN |= CKEN14_I2C;		/* set the global I2C clock on */
+	/* set the global I2C clock on */
+	writel(readl(CKEN) | CKEN14_I2C, CKEN);
 #endif
-	ISAR = I2C_PXA_SLAVE_ADDR;	/* set our slave address */
-	ICR = I2C_ICR_INIT;		/* set control register values */
-	ISR = I2C_ISR_INIT;		/* set clear interrupt bits */
-	ICR |= ICR_IUE;			/* enable unit */
+	writel(I2C_PXA_SLAVE_ADDR, ISAR);	/* set our slave address */
+	writel(I2C_ICR_INIT, ICR);		/* set control reg values */
+	writel(I2C_ISR_INIT, ISR);		/* set clear interrupt bits */
+	writel(readl(ICR) | ICR_IUE, ICR);	/* enable unit */
 	udelay(100);
 }
 
@@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
 			goto transfer_error_bus_busy;
 
 		/* start transmission */
-		ICR &= ~ICR_START;
-		ICR &= ~ICR_STOP;
-		IDBR = msg->data;
-		if (msg->condition == I2C_COND_START)     ICR |=  ICR_START;
-		if (msg->condition == I2C_COND_STOP)      ICR |=  ICR_STOP;
-		if (msg->acknack   == I2C_ACKNAK_SENDNAK) ICR |=  ICR_ACKNAK;
-		if (msg->acknack   == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
-		ICR &= ~ICR_ALDIE;
-		ICR |= ICR_TB;
+		writel(readl(ICR) & ~ICR_START, ICR);
+		writel(readl(ICR) & ~ICR_STOP, ICR);
+		writel(msg->data, IDBR);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(ICR) | ICR_START, ICR);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(ICR) | ICR_STOP, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(ICR) | ICR_ACKNAK, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+		writel(readl(ICR) & ~ICR_ALDIE, ICR);
+		writel(readl(ICR) | ICR_TB, ICR);
 
 		/* transmit register empty? */
 		if (!i2c_isr_set_cleared(ISR_ITE,0))
 			goto transfer_error_transmit_timeout;
 
 		/* clear 'transmit empty' state */
-		ISR |= ISR_ITE;
+		writel(readl(ISR) | ISR_ITE, ISR);
 
 		/* wait for ACK from slave */
 		if (msg->acknack == I2C_ACKNAK_WAITACK)
@@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
 			goto transfer_error_bus_busy;
 
 		/* start receive */
-		ICR &= ~ICR_START;
-		ICR &= ~ICR_STOP;
-		if (msg->condition == I2C_COND_START)	  ICR |= ICR_START;
-		if (msg->condition == I2C_COND_STOP)	  ICR |= ICR_STOP;
-		if (msg->acknack   == I2C_ACKNAK_SENDNAK) ICR |=  ICR_ACKNAK;
-		if (msg->acknack   == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
-		ICR &= ~ICR_ALDIE;
-		ICR |= ICR_TB;
+		writel(readl(ICR) & ~ICR_START, ICR);
+		writel(readl(ICR) & ~ICR_STOP, ICR);
+		if (msg->condition == I2C_COND_START)
+			writel(readl(ICR) | ICR_START, ICR);
+		if (msg->condition == I2C_COND_STOP)
+			writel(readl(ICR) | ICR_STOP, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDNAK)
+			writel(readl(ICR) | ICR_ACKNAK, ICR);
+		if (msg->acknack == I2C_ACKNAK_SENDACK)
+			writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+		writel(readl(ICR) & ~ICR_ALDIE, ICR);
+		writel(readl(ICR) | ICR_TB, ICR);
 
 		/* receive register full? */
 		if (!i2c_isr_set_cleared(ISR_IRF,0))
 			goto transfer_error_receive_timeout;
 
-		msg->data = IDBR;
+		msg->data = readl(IDBR);
 
 		/* clear 'receive empty' state */
-		ISR |= ISR_IRF;
+		writel(readl(ISR) | ISR_IRF, ISR);
 
 		break;
 

arch/arm/cpu/pxa/pxafb.c

@@ -35,6 +35,7 @@
 #include <stdio_dev.h>
 #include <lcd.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 /* #define DEBUG */
 
@@ -377,12 +378,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 4 bit data\n");
 		/* bits 58-61 */
-		GPDR1 |= (0xf << 26);
-		GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR1) | (0xf << 26), GPDR1);
+		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR1_U);
 
 		/* bits 74-77 */
-		GPDR2 |= (0xf << 10);
-		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR2) | (0xf << 10), GPDR2);
+		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR2_L);
 	}
 
 	/* 8 bit interface */
@@ -391,15 +394,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 8 bit data\n");
 		/* bits 58-65 */
-		GPDR1 |= (0x3f << 26);
-		GPDR2 |= (0x3);
+		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+		writel(readl(GPDR2) | (0x3), GPDR2);
 
-		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
-		GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
+		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+			GAFR1_U);
+		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 
 		/* bits 74-77 */
-		GPDR2 |= (0xf << 10);
-		GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+		writel(readl(GPDR2) | (0xf << 10), GPDR2);
+		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+			GAFR2_L);
 	}
 
 	/* 16 bit interface */
@@ -407,11 +412,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 	{
 		debug("Setting GPIO for 16 bit data\n");
 		/* bits 58-77 */
-		GPDR1 |= (0x3f << 26);
-		GPDR2 |= 0x00003fff;
+		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+		writel(readl(GPDR2) | 0x00003fff, GPDR2);
 
-		GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
-		GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
+		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+			GAFR1_U);
+		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 	}
 	else
 	{
@@ -425,26 +431,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
 	debug("Enabling LCD controller\n");
 
 	/* Sequence from 11.7.10 */
-	LCCR3  = vid->pxa.reg_lccr3;
-	LCCR2  = vid->pxa.reg_lccr2;
-	LCCR1  = vid->pxa.reg_lccr1;
-	LCCR0  = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
-	FDADR0 = vid->pxa.fdadr0;
-	FDADR1 = vid->pxa.fdadr1;
-	LCCR0 |= LCCR0_ENB;
+	writel(vid->pxa.reg_lccr3, LCCR3);
+	writel(vid->pxa.reg_lccr2, LCCR2);
+	writel(vid->pxa.reg_lccr1, LCCR1);
+	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
+	writel(vid->pxa.fdadr0, FDADR0);
+	writel(vid->pxa.fdadr1, FDADR1);
+	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 
 #ifdef	CONFIG_CPU_MONAHANS
-	CKENA |= CKENA_1_LCD;
+	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 #else
-	CKEN |= CKEN16_LCD;
+	writel(readl(CKEN) | CKEN16_LCD, CKEN);
 #endif
 
-	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
-	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
-	debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
-	debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
-	debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
-	debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
+	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
+	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
+	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
+	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
+	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
+	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 }
 
 static int pxafb_init (vidinfo_t *vid)

arch/arm/cpu/pxa/timer.c

@@ -26,8 +26,9 @@
  * MA 02111-1307 USA
  */
 
-#include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <common.h>
 #include <div64.h>
 
 #ifdef CONFIG_USE_IRQ
@@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
 
 void reset_timer_masked (void)
 {
-	OSCR = 0;
+	writel(0, OSCR);
 }
 
 ulong get_timer_masked (void)
@@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	return OSCR;
+	return readl(OSCR);
 }
 
 /*

arch/arm/cpu/pxa/usb.c

@@ -27,86 +27,79 @@
 # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 #include <usb.h>
 
 int usb_cpu_init(void)
 {
 #if defined(CONFIG_CPU_MONAHANS)
 	/* Enable USB host clock. */
-	CKENA |= (CKENA_2_USBHOST |  CKENA_20_UDC);
+	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
 	udelay(100);
 #endif
 #if defined(CONFIG_PXA27X)
 	/* Enable USB host clock. */
-	CKEN |= CKEN10_USBHOST;
+	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
 #endif
 
 #if defined(CONFIG_CPU_MONAHANS)
 	/* Configure Port 2 for Host (USB Client Registers) */
-	UP2OCR = 0x3000c;
+	writel(0x3000c, UP2OCR);
 #endif
 
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	wait_ms(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
-	while (UHCHR & UHCHR_FSBIR)
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
 		udelay(1);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR &= ~UHCHR_SSEP0;
+	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR &= ~UHCHR_SSEP2;
+	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
 #endif
-	UHCHR &= ~UHCHR_SSEP1;
-	UHCHR &= ~UHCHR_SSE;
+	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
 
 	return 0;
 }
 
 int usb_cpu_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
 	udelay(10);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR |= UHCHR_SSEP0;
+	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR |= UHCHR_SSEP2;
+	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
 #endif
-	UHCHR |= UHCHR_SSEP1;
-	UHCHR |= UHCHR_SSE;
-
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	UHCHR |= UHCHR_FHR;
-	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
-
-	UHCCOMS |= 1;
-	udelay(10);
+	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
 
 #if defined(CONFIG_CPU_MONAHANS)
-	UHCHR |= UHCHR_SSEP0;
+	/* Disable USB host clock. */
+	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+	udelay(100);
 #endif
 #if defined(CONFIG_PXA27X)
-	UHCHR |= UHCHR_SSEP2;
+	/* Disable USB host clock. */
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 #endif
-	UHCHR |= UHCHR_SSEP1;
-	UHCHR |= UHCHR_SSE;
 
 	return 0;
 }
 
+int usb_cpu_init_fail(void)
+{
+	return usb_cpu_stop();
+}
+
 # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

arch/arm/include/asm/arch-pxa/hardware.h

@@ -21,6 +21,19 @@
 #include <linux/config.h>
 #include <asm/mach-types.h>
 
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef	CONFIG_CPU_MONAHANS
+#if	defined(CONFIG_CPU_PXA300) || \
+	defined(CONFIG_CPU_PXA310) || \
+	defined(CONFIG_CPU_PXA320)
+#define	CONFIG_CPU_MONAHANS
+#endif
+#endif
 
 /*
  * These are statically mapped PCMCIA IO space for designs using it as a
@@ -51,54 +64,6 @@
  * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
  */
 
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-
-#ifndef UBOOT_REG_FIX
-#ifndef __ASSEMBLY__
-
-#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
-
-/*
- * This __REG() version gives the same results as the one above,  except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers.  It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x)	((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x)	__REGP(io_p2v(x))
-#endif
-
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y)	\
-	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
-
-# define __PREG(x)	(io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x)	io_p2v(x)
-# define __PREG(x)	io_v2p(x)
-
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)	   (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-#  ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
-#   define __REG_2(x) (x)
-#   define __REG_3(x) (x)
-#  endif
-# endif
-#endif /* UBOOT_REG_FIX */
-
 #include "pxa-regs.h"
 
 #ifndef __ASSEMBLY__

board/colibri_pxa270/colibri_pxa270.c

@@ -22,6 +22,7 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 #include <netdev.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,28 +66,30 @@ int dram_init (void)
 #ifdef	CONFIG_CMD_USB
 int usb_board_init(void)
 {
-	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
 	while (UHCHR & UHCHR_FSBIR);
 
-	UHCHR &= ~UHCHR_SSE;
-	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
 	/* Clear any OTG Pin Hold */
-	if (PSSR & PSSR_OTGPH)
-		PSSR |= PSSR_OTGPH;
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
 
-	UHCRHDA &= ~(0x200);
-	UHCRHDA |= 0x100;
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
 
 	/* Set port power control mask bits, only 3 ports. */
-	UHCRHDB |= (0x7<<17);
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 
 	/* enable port 2 */
-	UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
 
 	return 0;
 }
@@ -98,14 +101,14 @@ void usb_board_init_fail(void)
 
 void usb_board_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
 	udelay(10);
 
-	CKEN &= ~CKEN10_USBHOST;
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
 	return;
 }

board/cradle/cradle.c

@@ -28,6 +28,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
 #include <netdev.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,8 +93,8 @@ set_led (int led, int color)
 	int shift = led * 2;
 	unsigned long mask = 0x3 << shift;
 
-	CRADLE_LED_CLR_REG = mask;	/* clear bits */
-	CRADLE_LED_SET_REG = (color << shift);	/* set bits */
+	writel(mask, GPCR2);	/* clear bits */
+	writel((color << shift), GPSR2);	/* set bits */
 	udelay (5000);
 }
 

board/cradle/lowlevel_init.S

@@ -34,10 +34,10 @@ DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
    .endm
 
    .macro SET_LED val
-   ldr   r6, =CRADLE_LED_CLR_REG
+   ldr   r6, =GPCR2
    ldr   r7, =0
    str   r7, [r6]
-   ldr   r6, =CRADLE_LED_SET_REG
+   ldr   r6, =GPSR2
    ldr   r7, =\val
    str   r7, [r6]
    .endm

board/csb226/csb226.c

@@ -26,6 +26,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
 	switch(led) {
 
 		case 0: if (state==1) {
-				GPCR0 |= CSB226_USER_LED0;
+				writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
 			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED0;
+				writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
 			}
 			break;
 
 		case 1: if (state==1) {
-				GPCR0 |= CSB226_USER_LED1;
+				writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
 			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED1;
+				writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
 			}
 			break;
 
 		case 2: if (state==1) {
-				GPCR0 |= CSB226_USER_LED2;
+				writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
 			} else if (state==0) {
-				GPSR0 |= CSB226_USER_LED2;
+				writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
 			}
 			break;
 	}

board/delta/delta.c

@@ -28,6 +28,7 @@
 #include <malloc.h>
 #include <command.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
 static void get_pressed_keys(uchar *s)
 {
 	unsigned long val;
-	val = GPLR3;
+	val = readl(GPLR3);
 
 	if(val & (1<<31))
 		*s++ = KEYBD_KP_DKIN0;
@@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s)
 
 static void keys_init()
 {
-	CKENB |= CKENB_7_GPIO;
+	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
 	udelay(100);
 
 	/* Configure GPIOs */
-	GPIO127 = 0xa840;	/* KP_DKIN0 */
-	GPIO114 = 0xa840;	/* KP_DKIN1 */
-	GPIO125 = 0xa840;	/* KP_DKIN2 */
-	GPIO118 = 0xa840;	/* KP_DKIN5 */
+	writel(0xa840, GPIO127);	/* KP_DKIN0 */
+	writel(0xa840, GPIO114);	/* KP_DKIN1 */
+	writel(0xa840, GPIO125);	/* KP_DKIN2 */
+	writel(0xa840, GPIO118);	/* KP_DKIN5 */
 
 	/* Configure GPIOs as inputs */
-	GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
-	GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
+	writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
+	writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
 
 	udelay(100);
 }
@@ -283,11 +284,11 @@ int dram_init (void)
 
 void i2c_init_board()
 {
-	CKENB |= (CKENB_4_I2C);
+	writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
 
 	/* setup I2C GPIO's */
-	GPIO32 = 0x801;		/* SCL = Alt. Fkt. 1 */
-	GPIO33 = 0x801;		/* SDA = Alt. Fkt. 1 */
+	writel(0x801, GPIO32);		/* SCL = Alt. Fkt. 1 */
+	writel(0x801, GPIO33);		/* SDA = Alt. Fkt. 1 */
 }
 
 /* initialize the DA9030 Power Controller */
@@ -295,20 +296,20 @@ static void init_DA9030()
 {
 	uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
 
-	CKENB |= CKENB_7_GPIO;
+	writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
 	udelay(100);
 
 	/* Rising Edge on EXTON to reset DA9030 */
-	GPIO17 = 0x8800;	/* configure GPIO17, no pullup, -down */
-	GPDR0 |= (1<<17);	/* GPIO17 is output */
-	GSDR0 = (1<<17);
-	GPCR0 = (1<<17);	/* drive GPIO17 low */
-	GPSR0 = (1<<17);	/* drive GPIO17 high */
+	writel(0x8800, GPIO17);	/* configure GPIO17, no pullup, -down */
+	writel(readl(GPDR0) | (1<<17), GPDR0);	/* GPIO17 is output */
+	writel((1<<17), GSDR0);
+	writel((1<<17), GPCR0);	/* drive GPIO17 low */
+	writel((1<<17), GPSR0);	/* drive GPIO17 high */
 
 #if CONFIG_SYS_DA9030_EXTON_DELAY
 	udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY);	/* wait for DA9030 */
 #endif
-	GPCR0 = (1<<17);	/* drive GPIO17 low */
+	writel((1<<17), GPCR0);	/* drive GPIO17 low */
 
 	/* reset the watchdog and go active (0xec) */
 	val = (SYS_CONTROL_A_HWRES_ENABLE |

board/delta/nand.c

@@ -26,6 +26,7 @@
 
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_SYS_DFC_DEBUG1
 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 	if(bytes_multi) {
 		for(i=0; i<bytes_multi; i+=4) {
 			long_buf = (unsigned long*) &buf[i];
-			NDDB = *long_buf;
+			writel(*long_buf, NDDB);
 		}
 	}
 	if(rest) {
@@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 	if(bytes_multi) {
 		for(i=0; i<bytes_multi; i+=4) {
 			long_buf = (unsigned long*) &buf[i];
-			*long_buf = NDDB;
+			*long_buf = readl(NDDB);
 		}
 	}
 
@@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
 	unsigned long dummy;
 
 	if(bytes_read < 0) {
-		read_buf = NDDB;
-		dummy = NDDB;
+		read_buf = readl(NDDB);
+		dummy = readl(NDDB);
 		bytes_read = 0;
 	}
 	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
 /* calculate delta between OSCR values start and now  */
 static unsigned long get_delta(unsigned long start)
 {
-	unsigned long cur = OSCR;
+	unsigned long cur = readl(OSCR);
 
 	if(cur < start) /* OSCR overflowed */
 		return (cur + (start^0xffffffff));
@@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
 /* delay function, this doesn't belong here */
 static void wait_us(unsigned long us)
 {
-	unsigned long start = OSCR;
+	unsigned long start = readl(OSCR);
 	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
 
 	while (get_delta(start) < us) {
@@ -202,14 +203,14 @@ static void wait_us(unsigned long us)
 
 static void dfc_clear_nddb(void)
 {
-	NDCR &= ~NDCR_ND_RUN;
+	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
 	wait_us(CONFIG_SYS_NAND_OTHER_TO);
 }
 
 /* wait_event with timeout */
 static unsigned long dfc_wait_event(unsigned long event)
 {
-	unsigned long ndsr, timeout, start = OSCR;
+	unsigned long ndsr, timeout, start = readl(OSCR);
 
 	if(!event)
 		return 0xff000000;
@@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
 					* OSCR_CLK_FREQ, 1000);
 
 	while(1) {
-		ndsr = NDSR;
+		ndsr = readl(NDSR);
 		if(ndsr & event) {
-			NDSR |= event;
+			writel(readl(NDSR) | event, NDSR);
 			break;
 		}
 		if(get_delta(start) > timeout) {
@@ -243,11 +244,11 @@ static void dfc_new_cmd(void)
 
 	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
 		/* Clear NDSR */
-		NDSR = 0xFFF;
+		writel(0xfff, NDSR);
 
 		/* set NDCR[NDRUN] */
-		if(!(NDCR & NDCR_ND_RUN))
-			NDCR |= NDCR_ND_RUN;
+		if (!(readl(NDCR) & NDCR_ND_RUN))
+			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
 
 		status = dfc_wait_event(NDSR_WRCMDREQ);
 
@@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
 	}
 
  write_cmd:
-	NDCB0 = ndcb0;
-	NDCB0 = ndcb1;
-	NDCB0 = ndcb2;
+	writel(ndcb0, NDCB0);
+	writel(ndcb1, NDCB0);
+	writel(ndcb2, NDCB0);
 
 	/*  wait_event: */
 	dfc_wait_event(event);
@@ -372,36 +373,36 @@ static void dfc_gpio_init(void)
 	DFC_DEBUG2("Setting up DFC GPIO's.\n");
 
 	/* no idea what is done here, see zylonite.c */
-	GPIO4 = 0x1;
-
-	DF_ALE_WE1 = 0x00000001;
-	DF_ALE_WE2 = 0x00000001;
-	DF_nCS0 = 0x00000001;
-	DF_nCS1 = 0x00000001;
-	DF_nWE = 0x00000001;
-	DF_nRE = 0x00000001;
-	DF_IO0 = 0x00000001;
-	DF_IO8 = 0x00000001;
-	DF_IO1 = 0x00000001;
-	DF_IO9 = 0x00000001;
-	DF_IO2 = 0x00000001;
-	DF_IO10 = 0x00000001;
-	DF_IO3 = 0x00000001;
-	DF_IO11 = 0x00000001;
-	DF_IO4 = 0x00000001;
-	DF_IO12 = 0x00000001;
-	DF_IO5 = 0x00000001;
-	DF_IO13 = 0x00000001;
-	DF_IO6 = 0x00000001;
-	DF_IO14 = 0x00000001;
-	DF_IO7 = 0x00000001;
-	DF_IO15 = 0x00000001;
-
-	DF_nWE = 0x1901;
-	DF_nRE = 0x1901;
-	DF_CLE_NOE = 0x1900;
-	DF_ALE_WE1 = 0x1901;
-	DF_INT_RnB = 0x1900;
+	writel(0x1, GPIO4);
+
+	writel(0x00000001, DF_ALE_nWE1);
+	writel(0x00000001, DF_ALE_nWE2);
+	writel(0x00000001, DF_nCS0);
+	writel(0x00000001, DF_nCS1);
+	writel(0x00000001, DF_nWE);
+	writel(0x00000001, DF_nRE);
+	writel(0x00000001, DF_IO0);
+	writel(0x00000001, DF_IO8);
+	writel(0x00000001, DF_IO1);
+	writel(0x00000001, DF_IO9);
+	writel(0x00000001, DF_IO2);
+	writel(0x00000001, DF_IO10);
+	writel(0x00000001, DF_IO3);
+	writel(0x00000001, DF_IO11);
+	writel(0x00000001, DF_IO4);
+	writel(0x00000001, DF_IO12);
+	writel(0x00000001, DF_IO5);
+	writel(0x00000001, DF_IO13);
+	writel(0x00000001, DF_IO6);
+	writel(0x00000001, DF_IO14);
+	writel(0x00000001, DF_IO7);
+	writel(0x00000001, DF_IO15);
+
+	writel(0x1901, DF_nWE);
+	writel(0x1901, DF_nRE);
+	writel(0x1900, DF_CLE_nOE);
+	writel(0x1901, DF_ALE_nWE1);
+	writel(0x1900, DF_INT_RnB);
 }
 
 /*
@@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand)
 	dfc_gpio_init();
 
 	/* turn on the NAND Controller Clock (104 MHz @ D0) */
-	CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
 
 #undef CONFIG_SYS_TIMING_TIGHT
 #ifndef CONFIG_SYS_TIMING_TIGHT
@@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand)
 		tRP_high = 0;
 	}
 
-	NDTR0CS0 = (tCH << 19) |
+	writel((tCH << 19) |
 		(tCS << 16) |
 		(tWH << 11) |
 		(tWP << 8) |
 		(tRP_high << 6) |
 		(tRH << 3) |
-		(tRP << 0);
+		(tRP << 0),
+		NDTR0CS0);
 
-	NDTR1CS0 = (tR << 16) |
+	writel((tR << 16) |
 		(tWHR << 4) |
-		(tAR << 0);
+		(tAR << 0),
+		NDTR1CS0);
 
 	/* If it doesn't work (unlikely) think about:
 	 *  - ecc enable
@@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand)
 	 */
 	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
 
-	NDCR = (NDCR_SPARE_EN |		/* use the spare area */
+	writel(NDCR_SPARE_EN |		/* use the spare area */
 		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
 		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
 		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
@@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand)
 		NDCR_SBERRM |		/* single bit error ir masked */
 		NDCR_WRDREQM |		/* write data request ir masked */
 		NDCR_RDDREQM |		/* read data request ir masked */
-		NDCR_WRCMDREQM);	/* write command request ir masked */
+		NDCR_WRCMDREQM,		/* write command request ir masked */
+		NDCR);
 
 
 	/* wait 10 us due to cmd buffer clear reset */

board/innokom/innokom.c

@@ -27,6 +27,7 @@
 #include <netdev.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/mach-types.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,20 +49,21 @@ int i2c_init_board(void)
 
 	/* disable I2C controller first, otherwhise it thinks we want to    */
 	/* talk to the slave port...                                        */
-	icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+	icr = readl(ICR);
+	writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
 
 	/* set gpio pin low _before_ we change direction to output          */
-	GPCR(70) = GPIO_bit(70);
+	writel(GPIO_bit(70), GPCR(70));
 
 	/* now toggle between output=low and high-impedance                 */
 	for (i = 0; i < 20; i++) {
-		GPDR(70) |= GPIO_bit(70);  /* output */
+		writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70));  /* output */
 		udelay(10);
-		GPDR(70) &= ~GPIO_bit(70); /* input  */
+		writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input  */
 		udelay(10);
 	}
 
-	ICR = icr;
+	writel(icr, ICR);
 
 	return 0;
 }
@@ -76,7 +78,7 @@ int misc_init_r(void)
 	char *str;
 
 	/* determine if the software update key is pressed during startup   */
-	if (GPLR0 & 0x00000800) {
+	if (readl(GPLR0) & 0x00000800) {
 		printf("using bootcmd_normal (sw-update button not pressed)\n");
 		str = getenv("bootcmd_normal");
 	} else {

board/pxa255_idp/pxa_idp.c

@@ -33,6 +33,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <command.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,14 +57,14 @@ int board_init (void)
 
 	/* set PWM for LCD */
 	/* a value that works is 60Hz, 77% duty cycle */
-	CKEN |= CKEN0_PWM0;
-	PWM_CTRL0 = 0x3f;
-	PWM_PERVAL0 = 0x3ff;
-	PWM_PWDUTY0 = 792;
+	writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+	writel(0x3f, PWM_CTRL0);
+	writel(0x3ff, PWM_PERVAL0);
+	writel(792, PWM_PWDUTY0);
 
 	/* clear reset to AC97 codec */
-	CKEN |= CKEN2_AC97;
-	GCR = GCR_COLD_RST;
+	writel(readl(CKEN) | CKEN2_AC97, CKEN);
+	writel(GCR_COLD_RST, GCR);
 
 	/* enable LCD backlight */
 	/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
@@ -102,11 +103,11 @@ int dram_init (void)
 void delay_c(void)
 {
 	/* reset OSCR to 0 */
-	OSCR = 0;
-	while(OSCR > 0x10000)
+	writel(0, OSCR);
+	while (readl(OSCR) > 0x10000)
 		;
 
-	while(OSCR < 0xd4000)
+	while (readl(OSCR) < 0xd4000)
 		;
 }
 
@@ -114,12 +115,12 @@ void blink_c(void)
 {
 	int led_bit = (1<<10);
 
-	GPDR0 = led_bit;
-	GPCR0 = led_bit;
+	writel(led_bit, GPDR0);
+	writel(led_bit, GPCR0);
 	delay_c();
-	GPSR0 = led_bit;
+	writel(led_bit, GPSR0);
 	delay_c();
-	GPCR0 = led_bit;
+	writel(led_bit, GPCR0);
 }
 
 int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

board/trizepsiv/conxs.c

@@ -34,6 +34,7 @@
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 #include <netdev.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,25 +58,27 @@ extern struct serial_device serial_stuart_device;
 
 int usb_board_init(void)
 {
-	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
-	while (UHCHR & UHCHR_FSBIR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
 
-	UHCHR &= ~UHCHR_SSE;
-	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
 	/* Clear any OTG Pin Hold */
-	if (PSSR & PSSR_OTGPH)
-		PSSR |= PSSR_OTGPH;
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
 
-	UHCRHDA &= ~(RH_A_NPS);
-	UHCRHDA |= RH_A_PSM;
+	writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+	writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
 
 	/* Set port power control mask bits, only 3 ports. */
-	UHCRHDB |= (0x7<<17);
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 
 	return 0;
 }
@@ -87,14 +90,14 @@ void usb_board_init_fail(void)
 
 void usb_board_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
 	udelay(10);
 
-	CKEN &= ~CKEN10_USBHOST;
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
 	return;
 }

board/vpac270/vpac270.c

@@ -31,6 +31,8 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 #include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -75,28 +77,31 @@ int dram_init (void)
 
 int usb_board_init(void)
 {
-	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
 
-	UHCHR |= UHCHR_FSBIR;
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
-	while (UHCHR & UHCHR_FSBIR);
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		;
 
-	UHCHR &= ~UHCHR_SSE;
-	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
 	/* Clear any OTG Pin Hold */
-	if (PSSR & PSSR_OTGPH)
-		PSSR |= PSSR_OTGPH;
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
 
-	UHCRHDA &= ~(0x200);
-	UHCRHDA |= 0x100;
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
 
 	/* Set port power control mask bits, only 3 ports. */
-	UHCRHDB |= (0x7<<17);
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 
 	/* enable port 2 */
-	UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
 
 	return 0;
 }
@@ -108,14 +113,14 @@ void usb_board_init_fail(void)
 
 void usb_board_stop(void)
 {
-	UHCHR |= UHCHR_FHR;
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 	udelay(11);
-	UHCHR &= ~UHCHR_FHR;
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
-	UHCCOMS |= 1;
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
 	udelay(10);
 
-	CKEN &= ~CKEN10_USBHOST;
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
 	return;
 }

board/wepep250/wepep250.c

@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,13 +34,13 @@ int board_init (void)
  * Setup GPIO stuff to get serial working
  */
 #if defined( CONFIG_FFUART )
-	GPDR1 = 0x80;
-	GAFR1_L = 0x8010;
+	writel(0x80, GPDR1);
+	writel(0x8010, GAFR1_L);
 #elif defined( CONFIG_BTUART )
-	GPDR1 = 0x800;
-	GAFR1_L = 0x900000;
+	writel(0x800, GPDR1);
+	writel(0x900000, GAFR1_L);
 #endif
-	PSSR = 0x20;
+	writel(0x20, PSSR);
 
 	return 0;
 }

board/zipitz2/zipitz2.c

@@ -28,6 +28,7 @@
 #include <serial.h>
 #include <asm/arch/hardware.h>
 #include <spi.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set)
 {
 	/* GPIO 13 */
 	if (set)
-		GPSR0 = (1 << 13);
+		writel((1 << 13), GPSR0);
 	else
-		GPCR0 = (1 << 13);
+		writel((1 << 13), GPCR0);
 }
 
 void zipitz2_spi_scl(int set)
 {
 	/* GPIO 22 */
 	if (set)
-		GPCR0 = (1 << 22);
+		writel((1 << 22), GPCR0);
 	else
-		GPSR0 = (1 << 22);
+		writel((1 << 22), GPSR0);
 }
 
 unsigned char zipitz2_spi_read(void)
 {
 	/* GPIO 40 */
-	return !!(GPLR1 & (1 << 8));
+	return !!(readl(GPLR1) & (1 << 8));
 }
 
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 void spi_cs_activate(struct spi_slave *slave)
 {
 	/* GPIO 88 low */
-	GPCR2 = (1 << 24);
+	writel((1 << 24), GPCR2);
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	/* GPIO 88 high */
-	GPSR2 = (1 << 24);
+	writel((1 << 24), GPSR2);
 
 }
 
@@ -176,20 +177,20 @@ void lcd_start(void)
 	unsigned char dummy[3] = { 0, 0, 0 };
 
 	/* PWM2 AF */
-	GAFR0_L |= 0x00800000;
+	writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
 	/* Enable clock to all PWM */
-	CKEN |= 0x3;
+	writel(readl(CKEN) | 0x3, CKEN);
 	/* Configure PWM2 */
-	PWM_CTRL2 = 0x4f;
-	PWM_PWDUTY2 = 0x2ff;
-	PWM_PERVAL2 = 792;
+	writel(0x4f, PWM_CTRL2);
+	writel(0x2ff, PWM_PWDUTY2);
+	writel(792, PWM_PERVAL2);
 
 	/* Toggle the reset pin to reset the LCD */
-	GPSR0 = (1 << 19);
+	writel((1 << 19), GPSR0);
 	udelay(100000);
-	GPCR0 = (1 << 19);
+	writel((1 << 19), GPCR0);
 	udelay(20000);
-	GPSR0 = (1 << 19);
+	writel((1 << 19), GPSR0);
 	udelay(20000);
 
 	/* Program the LCD init sequence */
@@ -208,6 +209,6 @@ void lcd_start(void)
 			udelay(lcd_data[i].mdelay * 1000);
 	}
 
-	GPSR0 = (1 << 11);
+	writel((1 << 11), GPSR0);
 }
 #endif

board/zylonite/nand.c

@@ -21,6 +21,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NAND)
 
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 	if(bytes_multi) {
 		for(i=0; i<bytes_multi; i+=4) {
 			long_buf = (unsigned long*) &buf[i];
-			NDDB = *long_buf;
+			writel(*long_buf, NDDB);
 		}
 	}
 	if(rest) {
@@ -125,7 +126,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 	if(bytes_multi) {
 		for(i=0; i<bytes_multi; i+=4) {
 			long_buf = (unsigned long*) &buf[i];
-			*long_buf = NDDB;
+			*long_buf = readl(NDDB);
 		}
 	}
 
@@ -171,8 +172,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
 	unsigned long dummy;
 
 	if(bytes_read < 0) {
-		read_buf = NDDB;
-		dummy = NDDB;
+		read_buf = readl(NDDB);
+		dummy = readl(NDDB);
 		bytes_read = 0;
 	}
 	byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
 /* calculate delta between OSCR values start and now  */
 static unsigned long get_delta(unsigned long start)
 {
-	unsigned long cur = OSCR;
+	unsigned long cur = readl(OSCR);
 
 	if(cur < start) /* OSCR overflowed */
 		return (cur + (start^0xffffffff));
@@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
 /* delay function, this doesn't belong here */
 static void wait_us(unsigned long us)
 {
-	unsigned long start = OSCR;
+	unsigned long start = readl(OSCR);
 	us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
 
 	while (get_delta(start) < us) {
@@ -207,14 +208,14 @@ static void wait_us(unsigned long us)
 
 static void dfc_clear_nddb(void)
 {
-	NDCR &= ~NDCR_ND_RUN;
+	writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
 	wait_us(CONFIG_SYS_NAND_OTHER_TO);
 }
 
 /* wait_event with timeout */
 static unsigned long dfc_wait_event(unsigned long event)
 {
-	unsigned long ndsr, timeout, start = OSCR;
+	unsigned long ndsr, timeout, start = readl(OSCR);
 
 	if(!event)
 		return 0xff000000;
@@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event)
 					* OSCR_CLK_FREQ, 1000);
 
 	while(1) {
-		ndsr = NDSR;
+		ndsr = readl(NDSR);
 		if(ndsr & event) {
-			NDSR |= event;
+			writel(readl(NDSR) | event, NDSR);
 			break;
 		}
 		if(get_delta(start) > timeout) {
@@ -248,11 +249,11 @@ static void dfc_new_cmd(void)
 
 	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
 		/* Clear NDSR */
-		NDSR = 0xFFF;
+		writel(0xFFF, NDSR);
 
 		/* set NDCR[NDRUN] */
-		if(!(NDCR & NDCR_ND_RUN))
-			NDCR |= NDCR_ND_RUN;
+		if (!(readl(NDCR) & NDCR_ND_RUN))
+			writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
 
 		status = dfc_wait_event(NDSR_WRCMDREQ);
 
@@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
 	}
 
  write_cmd:
-	NDCB0 = ndcb0;
-	NDCB0 = ndcb1;
-	NDCB0 = ndcb2;
+	writel(ndcb0, NDCB0);
+	writel(ndcb1, NDCB0);
+	writel(ndcb2, NDCB0);
 
 	/*  wait_event: */
 	dfc_wait_event(event);
@@ -377,36 +378,36 @@ static void dfc_gpio_init(void)
 	DFC_DEBUG2("Setting up DFC GPIO's.\n");
 
 	/* no idea what is done here, see zylonite.c */
-	GPIO4 = 0x1;
-
-	DF_ALE_WE1 = 0x00000001;
-	DF_ALE_WE2 = 0x00000001;
-	DF_nCS0 = 0x00000001;
-	DF_nCS1 = 0x00000001;
-	DF_nWE = 0x00000001;
-	DF_nRE = 0x00000001;
-	DF_IO0 = 0x00000001;
-	DF_IO8 = 0x00000001;
-	DF_IO1 = 0x00000001;
-	DF_IO9 = 0x00000001;
-	DF_IO2 = 0x00000001;
-	DF_IO10 = 0x00000001;
-	DF_IO3 = 0x00000001;
-	DF_IO11 = 0x00000001;
-	DF_IO4 = 0x00000001;
-	DF_IO12 = 0x00000001;
-	DF_IO5 = 0x00000001;
-	DF_IO13 = 0x00000001;
-	DF_IO6 = 0x00000001;
-	DF_IO14 = 0x00000001;
-	DF_IO7 = 0x00000001;
-	DF_IO15 = 0x00000001;
-
-	DF_nWE = 0x1901;
-	DF_nRE = 0x1901;
-	DF_CLE_NOE = 0x1900;
-	DF_ALE_WE1 = 0x1901;
-	DF_INT_RnB = 0x1900;
+	writel(0x1, GPIO4);
+
+	writel(0x00000001, DF_ALE_nWE1);
+	writel(0x00000001, DF_ALE_nWE2);
+	writel(0x00000001, DF_nCS0);
+	writel(0x00000001, DF_nCS1);
+	writel(0x00000001, DF_nWE);
+	writel(0x00000001, DF_nRE);
+	writel(0x00000001, DF_IO0);
+	writel(0x00000001, DF_IO8);
+	writel(0x00000001, DF_IO1);
+	writel(0x00000001, DF_IO9);
+	writel(0x00000001, DF_IO2);
+	writel(0x00000001, DF_IO10);
+	writel(0x00000001, DF_IO3);
+	writel(0x00000001, DF_IO11);
+	writel(0x00000001, DF_IO4);
+	writel(0x00000001, DF_IO12);
+	writel(0x00000001, DF_IO5);
+	writel(0x00000001, DF_IO13);
+	writel(0x00000001, DF_IO6);
+	writel(0x00000001, DF_IO14);
+	writel(0x00000001, DF_IO7);
+	writel(0x00000001, DF_IO15);
+
+	writel(0x1901, DF_nWE);
+	writel(0x1901, DF_nRE);
+	writel(0x1900, DF_CLE_nOE);
+	writel(0x1901, DF_ALE_nWE1);
+	writel(0x1900, DF_INT_RnB);
 }
 
 /*
@@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand)
 	dfc_gpio_init();
 
 	/* turn on the NAND Controller Clock (104 MHz @ D0) */
-	CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+	writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
 
 #undef CONFIG_SYS_TIMING_TIGHT
 #ifndef CONFIG_SYS_TIMING_TIGHT
@@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand)
 		tRP_high = 0;
 	}
 
-	NDTR0CS0 = (tCH << 19) |
+	writel((tCH << 19) |
 		(tCS << 16) |
 		(tWH << 11) |
 		(tWP << 8) |
 		(tRP_high << 6) |
 		(tRH << 3) |
-		(tRP << 0);
+		(tRP << 0),
+		NDTR0CS0);
 
-	NDTR1CS0 = (tR << 16) |
+	writel((tR << 16) |
 		(tWHR << 4) |
-		(tAR << 0);
+		(tAR << 0),
+		NDTR1CS0);
 
 	/* If it doesn't work (unlikely) think about:
 	 *  - ecc enable
@@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand)
 	 */
 	/* NDCR_NCSX |		/\* Chip select busy don't care *\/ */
 
-	NDCR = (NDCR_SPARE_EN |		/* use the spare area */
+	writel(NDCR_SPARE_EN |		/* use the spare area */
 		NDCR_DWIDTH_C |		/* 16bit DFC data bus width  */
 		NDCR_DWIDTH_M |		/* 16 bit Flash device data bus width */
 		(2 << 16) |		/* read id count = 7 ???? mk@tbd */
@@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand)
 		NDCR_SBERRM |		/* single bit error ir masked */
 		NDCR_WRDREQM |		/* write data request ir masked */
 		NDCR_RDDREQM |		/* read data request ir masked */
-		NDCR_WRCMDREQM);	/* write command request ir masked */
+		NDCR_WRCMDREQM,		/* write command request ir masked */
+		NDCR);
 
 
 	/* wait 10 us due to cmd buffer clear reset */

drivers/mmc/pxa_mmc.c

@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/hardware.h>
 #include <part.h>
+#include <asm/io.h>
 
 #include "pxa_mmc.h"
 
@@ -59,18 +60,20 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 
 	debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
 	      cmdat | wide);
-	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
-	MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
-	while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ;
-	MMC_CMD = cmd;
-	MMC_ARGH = argh;
-	MMC_ARGL = argl;
-	MMC_CMDAT = cmdat | wide;
-	MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
-	MMC_STRPCL = MMC_STRPCL_START_CLK;
-	while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ;
-
-	status = MMC_STAT;
+	writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+	writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
+	while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
+		;
+	writel(cmd, MMC_CMD);
+	writel(argh, MMC_ARGH);
+	writel(argl, MMC_ARGL);
+	writel(cmdat | wide, MMC_CMDAT);
+	writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
+	writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
+	while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
+		;
+
+	status = readl(MMC_STAT);
 	debug("MMC status 0x%08x\n", status);
 	if (status & MMC_STAT_TIME_OUT_RESPONSE) {
 		return 0;
@@ -80,10 +83,10 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
 	 * Did I mention this is Sick.  We always need to
 	 * discard the upper 8 bits of the first 16-bit word.
 	 */
-	a = (MMC_RES & 0xffff);
+	a = (readl(MMC_RES) & 0xffff);
 	for (i = 0; i < 4; i++) {
-		b = (MMC_RES & 0xffff);
-		c = (MMC_RES & 0xffff);
+		b = (readl(MMC_RES) & 0xffff);
+		c = (readl(MMC_RES) & 0xffff);
 		resp[i] = (a << 24) | (b << 8) | (c >> 8);
 		a = c;
 		debug("MMC resp[%d] = %#08x\n", i, resp[i]);
@@ -115,37 +118,38 @@ mmc_block_read(uchar * dst, ulong src, ulong len)
 	/* send read command */
 	argh = src >> 16;
 	argl = src & 0xffff;
-	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
-	MMC_RDTO = 0xffff;
-	MMC_NOB = 1;
-	MMC_BLKLEN = len;
+	writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+	writel(0xffff, MMC_RDTO);
+	writel(1, MMC_NOB);
+	writel(len, MMC_BLKLEN);
 	mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
 		MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
 		MMC_CMDAT_DATA_EN);
 
-	MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
+	writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
 	while (len) {
-		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+		if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 			int i;
 			for (i = min(len, 32); i; i--) {
-				*dst++ = *((volatile uchar *)&MMC_RXFIFO);
+				*dst++ = readb(MMC_RXFIFO);
 				len--;
 			}
 #else
-			*dst++ = MMC_RXFIFO;
+			*dst++ = readb(MMC_RXFIFO);
 			len--;
 #endif
 		}
-		status = MMC_STAT;
+		status = readl(MMC_STAT);
 		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
 	}
-	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
-	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
-	status = MMC_STAT;
+	writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+	while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+		;
+	status = readl(MMC_STAT);
 	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
@@ -176,37 +180,39 @@ mmc_block_write(ulong dst, uchar * src, int len)
 	/* send write command */
 	argh = dst >> 16;
 	argl = dst & 0xffff;
-	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
-	MMC_NOB = 1;
-	MMC_BLKLEN = len;
+	writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+	writel(1, MMC_NOB);
+	writel(len, MMC_BLKLEN);
 	mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
 		MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
 		MMC_CMDAT_DATA_EN);
 
-	MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
+	writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
 	while (len) {
-		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
+		if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
 			int i, bytes = min(32, len);
 
 			for (i = 0; i < bytes; i++) {
-				MMC_TXFIFO = *src++;
+				writel(*src++, MMC_TXFIFO);
 			}
 			if (bytes < 32) {
-				MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
+				writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
 			}
 			len -= bytes;
 		}
-		status = MMC_STAT;
+		status = readl(MMC_STAT);
 		if (status & MMC_STAT_ERRORS) {
 			printf("MMC_STAT error %lx\n", status);
 			return -1;
 		}
 	}
-	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
-	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
-	MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
-	while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ;
-	status = MMC_STAT;
+	writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+	while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+		;
+	writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
+	while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
+		;
+	status = readl(MMC_STAT);
 	if (status & MMC_STAT_ERRORS) {
 		printf("MMC_STAT error %lx\n", status);
 		return -1;
@@ -559,13 +565,13 @@ mmc_legacy_init(int verbose)
 	set_GPIO_mode(GPIO8_MMCCS0_MD);
 #endif
 #ifdef CONFIG_CPU_MONAHANS	/* pxa3xx */
-	CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1;
+	writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
 #else	/* pxa2xx */
-	CKEN |= CKEN12_MMC;	/* enable MMC unit clock */
+	writel(readl(CKEN) | CKEN12_MMC, CKEN);	/* enable MMC unit clock */
 #endif
-	MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
-	MMC_RESTO = MMC_RES_TO_MAX;
-	MMC_SPI = MMC_SPI_DISABLE;
+	writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
+	writel(MMC_RES_TO_MAX, MMC_RESTO);
+	writel(MMC_SPI_DISABLE, MMC_SPI);
 
 	/* reset */
 	mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
@@ -624,7 +630,7 @@ mmc_legacy_init(int verbose)
 		mmc_decode_cid(cid_resp);
 	}
 
-	MMC_CLKRT = 0;		/* 20 MHz */
+	writel(0, MMC_CLKRT);		/* 20 MHz */
 	resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
 
 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)

drivers/serial/serial_pxa.c

@@ -32,6 +32,7 @@
 #include <watchdog.h>
 #include <serial.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -73,60 +74,60 @@ void pxa_setbrg_dev (unsigned int uart_index)
 	switch (uart_index) {
 		case FFUART_INDEX:
 #ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_22_FFUART;
+			writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
 #else
-			CKEN |= CKEN6_FFUART;
+			writel(readl(CKEN) | CKEN6_FFUART, CKEN);
 #endif /* CONFIG_CPU_MONAHANS */
 
-			FFIER = 0;	/* Disable for now */
-			FFFCR = 0;	/* No fifos enabled */
+			writel(0, FFIER);	/* Disable for now */
+			writel(0, FFFCR);	/* No fifos enabled */
 
 			/* set baud rate */
-			FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-			FFDLL = quot & 0xff;
-			FFDLH = quot >> 8;
-			FFLCR = LCR_WLS0 | LCR_WLS1;
+			writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
+			writel(quot & 0xff, FFDLL);
+			writel(quot >> 8, FFDLH);
+			writel(LCR_WLS0 | LCR_WLS1, FFLCR);
 
-			FFIER = IER_UUE;	/* Enable FFUART */
+			writel(IER_UUE, FFIER);	/* Enable FFUART */
 		break;
 
 		case BTUART_INDEX:
 #ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_21_BTUART;
+			writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
 #else
-			CKEN |= CKEN7_BTUART;
+			writel(readl(CKEN) | CKEN7_BTUART, CKEN);
 #endif /*  CONFIG_CPU_MONAHANS */
 
-			BTIER = 0;
-			BTFCR = 0;
+			writel(0, BTIER);
+			writel(0, BTFCR);
 
 			/* set baud rate */
-			BTLCR = LCR_DLAB;
-			BTDLL = quot & 0xff;
-			BTDLH = quot >> 8;
-			BTLCR = LCR_WLS0 | LCR_WLS1;
+			writel(LCR_DLAB, BTLCR);
+			writel(quot & 0xff, BTDLL);
+			writel(quot >> 8, BTDLH);
+			writel(LCR_WLS0 | LCR_WLS1, BTLCR);
 
-			BTIER = IER_UUE;	/* Enable BFUART */
+			writel(IER_UUE, BTIER);	/* Enable BFUART */
 
 		break;
 
 		case STUART_INDEX:
 #ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_23_STUART;
+			writel(readl(CKENA) | CKENA_23_STUART, CKENA);
 #else
-			CKEN |= CKEN5_STUART;
+			writel(readl(CKEN) | CKEN5_STUART, CKEN);
 #endif /* CONFIG_CPU_MONAHANS */
 
-			STIER = 0;
-			STFCR = 0;
+			writel(0, STIER);
+			writel(0, STFCR);
 
 			/* set baud rate */
-			STLCR = LCR_DLAB;
-			STDLL = quot & 0xff;
-			STDLH = quot >> 8;
-			STLCR = LCR_WLS0 | LCR_WLS1;
+			writel(LCR_DLAB, STLCR);
+			writel(quot & 0xff, STDLL);
+			writel(quot >> 8, STDLH);
+			writel(LCR_WLS0 | LCR_WLS1, STLCR);
 
-			STIER = IER_UUE;			/* Enable STUART */
+			writel(IER_UUE, STIER);	/* Enable STUART */
 			break;
 
 		default:
@@ -156,21 +157,21 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
 	switch (uart_index) {
 		case FFUART_INDEX:
 		/* wait for room in the tx FIFO on FFUART */
-			while ((FFLSR & LSR_TEMT) == 0)
+			while ((readl(FFLSR) & LSR_TEMT) == 0)
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			FFTHR = c;
+			writel(c, FFTHR);
 			break;
 
 		case BTUART_INDEX:
-			while ((BTLSR & LSR_TEMT ) == 0 )
+			while ((readl(BTLSR) & LSR_TEMT) == 0)
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			BTTHR = c;
+			writel(c, BTTHR);
 			break;
 
 		case STUART_INDEX:
-			while ((STLSR & LSR_TEMT ) == 0 )
+			while ((readl(STLSR) & LSR_TEMT) == 0)
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			STTHR = c;
+			writel(c, STTHR);
 			break;
 	}
 
@@ -188,11 +189,11 @@ int pxa_tstc_dev (unsigned int uart_index)
 {
 	switch (uart_index) {
 		case FFUART_INDEX:
-			return FFLSR & LSR_DR;
+			return readl(FFLSR) & LSR_DR;
 		case BTUART_INDEX:
-			return BTLSR & LSR_DR;
+			return readl(BTLSR) & LSR_DR;
 		case STUART_INDEX:
-			return STLSR & LSR_DR;
+			return readl(STLSR) & LSR_DR;
 	}
 	return -1;
 }
@@ -206,18 +207,21 @@ int pxa_getc_dev (unsigned int uart_index)
 {
 	switch (uart_index) {
 		case FFUART_INDEX:
-			while (!(FFLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) FFRBR & 0xff;
+			while (!(readl(FFLSR) & LSR_DR))
+				/* Reset HW Watchdog, if needed */
+				WATCHDOG_RESET();
+			return (char) readl(FFRBR) & 0xff;
 
 		case BTUART_INDEX:
-			while (!(BTLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) BTRBR & 0xff;
+			while (!(readl(BTLSR) & LSR_DR))
+				/* Reset HW Watchdog, if needed */
+				WATCHDOG_RESET();
+			return (char) readl(BTRBR) & 0xff;
 		case STUART_INDEX:
-			while (!(STLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) STRBR & 0xff;
+			while (!(readl(STLSR) & LSR_DR))
+				/* Reset HW Watchdog, if needed */
+				WATCHDOG_RESET();
+			return (char) readl(STRBR) & 0xff;
 	}
 	return -1;
 }

include/configs/cradle.h

@@ -339,8 +339,6 @@
 #define LED_IRDA1 2
 #define LED_IRDA2 4
 #define LED_IRDA3 6
-#define CRADLE_LED_SET_REG GPSR2
-#define CRADLE_LED_CLR_REG GPCR2
 
 /* SuperIO defines */
 #define CRADLE_SIO_INDEX      0x2e

include/configs/delta.h

@@ -28,6 +28,7 @@
  * (easy to change)
  */
 #define CONFIG_CPU_MONAHANS	1	/* Intel Monahan CPU    */
+#define	CONFIG_CPU_PXA320
 #define CONFIG_DELTA		1	/* Delta board       */
 
 /* #define CONFIG_LCD		1 */

include/configs/zylonite.h

@@ -35,6 +35,7 @@
  * (easy to change)
  */
 #define CONFIG_CPU_MONAHANS	1	/* Intel Monahan CPU    */
+#define	CONFIG_CPU_PXA320
 #define CONFIG_ZYLONITE		1	/* Zylonite board       */
 
 /* #define CONFIG_LCD		1 */