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@@ -41,6 +41,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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+#include <asm/arch/dma.h>
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struct mxsmmc_priv {
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int id;
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@@ -49,6 +50,7 @@ struct mxsmmc_priv {
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uint32_t *clkctrl_ssp;
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uint32_t buswidth;
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int (*mmc_is_wp)(int);
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+ struct mxs_dma_desc *desc;
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};
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#define MXSMMC_MAX_TIMEOUT 10000
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@@ -64,8 +66,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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struct mx28_ssp_regs *ssp_regs = priv->regs;
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uint32_t reg;
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int timeout;
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- uint32_t data_count;
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- uint32_t *data_ptr;
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+ uint32_t data_count, cache_data_count;
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uint32_t ctrl0;
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debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
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@@ -183,40 +184,41 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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if (!data)
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return 0;
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- /* Process the data */
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data_count = data->blocksize * data->blocks;
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- timeout = MXSMMC_MAX_TIMEOUT;
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+
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+ if (data_count % ARCH_DMA_MINALIGN)
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+ cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
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+ else
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+ cache_data_count = data_count;
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+
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if (data->flags & MMC_DATA_READ) {
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- data_ptr = (uint32_t *)data->dest;
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- while (data_count && --timeout) {
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- reg = readl(&ssp_regs->hw_ssp_status);
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- if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
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- *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
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- data_count -= 4;
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- timeout = MXSMMC_MAX_TIMEOUT;
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- } else
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- udelay(1000);
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- }
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+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
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+ priv->desc->cmd.address = (dma_addr_t)data->dest;
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} else {
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- data_ptr = (uint32_t *)data->src;
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- timeout *= 100;
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- while (data_count && --timeout) {
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- reg = readl(&ssp_regs->hw_ssp_status);
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- if (!(reg & SSP_STATUS_FIFO_FULL)) {
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- writel(*data_ptr++, &ssp_regs->hw_ssp_data);
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- data_count -= 4;
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- timeout = MXSMMC_MAX_TIMEOUT;
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- } else
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- udelay(1000);
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- }
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+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
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+ priv->desc->cmd.address = (dma_addr_t)data->src;
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+
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+ /* Flush data to DRAM so DMA can pick them up */
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+ flush_dcache_range((uint32_t)priv->desc->cmd.address,
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+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
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}
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- if (!timeout) {
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- printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
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- mmc->block_dev.dev, cmd->cmdidx, reg);
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+ priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
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+ (data_count << MXS_DMA_DESC_BYTES_OFFSET);
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+
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+
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+ mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
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+ if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
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+ printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
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return COMM_ERR;
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}
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+ /* The data arrived into DRAM, invalidate cache over them */
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+ if (data->flags & MMC_DATA_READ) {
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+ invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
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+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
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+ }
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+
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/* Check data errors */
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reg = readl(&ssp_regs->hw_ssp_status);
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if (reg &
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@@ -270,7 +272,8 @@ static int mxsmmc_init(struct mmc *mmc)
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/* 8 bits word length in MMC mode */
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clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
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SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
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- SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
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+ SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
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+ SSP_CTRL1_DMA_ENABLE);
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/* Set initial bit clock 400 KHz */
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mx28_set_ssp_busclock(priv->id, 400);
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@@ -300,6 +303,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
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return -ENOMEM;
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}
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+ priv->desc = mxs_dma_desc_alloc();
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+ if (!priv->desc) {
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+ free(priv);
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+ free(mmc);
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+ return -ENOMEM;
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+ }
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+
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priv->mmc_is_wp = wp;
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priv->id = id;
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switch (id) {
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@@ -345,7 +355,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
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*/
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mmc->f_min = 400000;
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mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
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- mmc->b_max = 0;
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+ mmc->b_max = 0x40;
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mmc_register(mmc);
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return 0;
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