vf610: Add QSPI support for VF610TWR

Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -163,6 +163,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)			(((v) & 0x3) << 22)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
@@ -174,6 +177,11 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_QSPI0_EN			(1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)			((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)		((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)		((v) & 0x3)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -105,6 +105,8 @@
 #define QSPI1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00044000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 
+#define QSPI0_AMBA_BASE		0x20000000
+
 /*GPIO*/
 #define GPIO2_PSOR          (0x400FF084)
 /* MUX mode and PAD ctrl are in one register */

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -35,9 +35,8 @@
 				PAD_CTL_INPUT_DIFFERENTIAL)
 #define VF610_USB_PAD_CTRL	(PAD_CTL_PUS_100K_UP | \
 				PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-
-#define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_50ohm | \
-				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+				PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_NFC_PAD_CTRL	(PAD_CTL_SPEED_HIGH | \
 				PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
 
@@ -110,18 +109,18 @@ enum {
 	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_PTD6__GPIO85			= IOMUX_PAD(0x0154, 0x0154, 0, __NA_, 0, VF610_USB_PAD_CTRL),
 	VF610_PAD_PTD13__GPIO92			= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-	VF610_PAD_PTD0__QSCKA			= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD1__QCS0A			= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD2__QIO3A			= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD3__QIO2A			= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD4__QIO1A			= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD5__QIO0A			= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD7__QSCKB			= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD8__QCS0B			= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD9__QIO3B			= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD10__QIO2B			= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD11__QIO1B			= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
-	VF610_PAD_PTD12__QIO0B			= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD8__QSPI0_B_CS0		= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__QSPI0_B_DATA3		= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD10__QSPI0_B_DATA2		= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD11__QSPI0_B_DATA1		= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD12__QSPI0_B_DATA0		= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTA19__QSCKA			= IOMUX_PAD(0x0024, 0x0024, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTB0__QCS0A			= IOMUX_PAD(0x0058, 0x0058, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_PTB1__QIO3A			= IOMUX_PAD(0x005C, 0x005C, 7, __NA_, 0, VF610_QSPI_PAD_CTRL),

board/freescale/vf610twr/vf610twr.c

@@ -315,6 +315,26 @@ static void setup_iomux_enet(void)
 	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 }
 
+static void setup_iomux_qspi(void)
+{
+	static const iomux_v3_cfg_t qspi0_pads[] = {
+		VF610_PAD_PTD0__QSPI0_A_QSCK,
+		VF610_PAD_PTD1__QSPI0_A_CS0,
+		VF610_PAD_PTD2__QSPI0_A_DATA3,
+		VF610_PAD_PTD3__QSPI0_A_DATA2,
+		VF610_PAD_PTD4__QSPI0_A_DATA1,
+		VF610_PAD_PTD5__QSPI0_A_DATA0,
+		VF610_PAD_PTD7__QSPI0_B_QSCK,
+		VF610_PAD_PTD8__QSPI0_B_CS0,
+		VF610_PAD_PTD9__QSPI0_B_DATA3,
+		VF610_PAD_PTD10__QSPI0_B_DATA2,
+		VF610_PAD_PTD11__QSPI0_B_DATA1,
+		VF610_PAD_PTD12__QSPI0_B_DATA0,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},
@@ -409,11 +429,14 @@ static void clock_init(void)
 		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 		CCM_CACRR_ARM_CLK_DIV(0));
 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
-		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 		CCM_CSCDR1_RMII_CLK_EN);
 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+		CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+		CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 		CCM_CSCMR2_RMII_CLK_SEL(0));
 }
@@ -442,6 +465,7 @@ int board_early_init_f(void)
 
 	setup_iomux_uart();
 	setup_iomux_enet();
+	setup_iomux_qspi();
 
 	return 0;
 }

include/configs/vf610twr.h

@@ -138,6 +138,18 @@
 #define CONFIG_FEC_MXC_PHYADDR          0
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
+
+/* QSPI Configs*/
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+
 #define CONFIG_ETHADDR			00:e0:0c:bc:e5:60
 #define CONFIG_BOOTDELAY		3
 
@@ -283,6 +295,4 @@
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_VF610_QSPI
-
 #endif