vf610: Code style fixes

board/freescale/vf610twr/vf610twr.c

@@ -372,21 +372,21 @@ static void clock_init(void)
         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
                 CCM_CCGRX_ENABLE_ALL_CTRL_MASK);
 
-	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
-		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
-
 #ifdef CONFIG_VF610_500MHZ
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL3_CTRL_BYPASS |
-			ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE |
-			ANADIG_PLL2_CTRL_DIV_SELECT);
+		ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE |
+		ANADIG_PLL2_CTRL_DIV_SELECT);
 #else
 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
-			ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
 #endif
 
 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+
 #ifdef CONFIG_VF610_500MHZ
 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
 		CCM_CCSR_PLL1_PFD_CLK_SEL(1) | CCM_CCSR_PLL2_PFD4_EN |