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@@ -87,6 +87,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
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val = readl(&emif_regs->NANDFCR);
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+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
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writel(val, &emif_regs->NANDFCR);
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}
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@@ -219,6 +220,7 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
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*/
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val = readl(&emif_regs->NANDFCR);
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val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
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+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_4BIT_ECC_START;
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writel(val, &emif_regs->NANDFCR);
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