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@@ -82,26 +82,20 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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- int dummy;
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+ u_int32_t val;
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- dummy = emif_regs->NANDF1ECC;
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+ (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
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- /* FIXME: only chipselect 0 is supported for now */
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- emif_regs->NANDFCR |= 1 << 8;
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+ val = readl(&emif_regs->NANDFCR);
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+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
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+ writel(val, &emif_regs->NANDFCR);
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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{
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u_int32_t ecc = 0;
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- if (region == 1)
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- ecc = emif_regs->NANDF1ECC;
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- else if (region == 2)
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- ecc = emif_regs->NANDF2ECC;
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- else if (region == 3)
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- ecc = emif_regs->NANDF3ECC;
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- else if (region == 4)
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- ecc = emif_regs->NANDF4ECC;
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+ ecc = readl(&(emif_regs->NANDFECC[region - 1]));
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return(ecc);
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}
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@@ -223,8 +217,11 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
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* Start a new ECC calculation for reading or writing 512 bytes
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* of data.
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*/
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- val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
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- emif_regs->NANDFCR = val;
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+ val = readl(&emif_regs->NANDFCR);
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+ val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
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+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
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+ val |= DAVINCI_NANDFCR_4BIT_ECC_START;
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+ writel(val, &emif_regs->NANDFCR);
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break;
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case NAND_ECC_READSYN:
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val = emif_regs->NAND4BITECC1;
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