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@@ -1,5 +1,5 @@
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/*
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/*
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- * (C) Copyright 2009 Freescale Semiconductor, Inc.
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+ * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
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*
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*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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*
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@@ -26,6 +26,7 @@
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#include <usb.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <usb/ehci-fsl.h>
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#include <usb/ehci-fsl.h>
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+#include <hwconfig.h>
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#include "ehci.h"
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#include "ehci.h"
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#include "ehci-core.h"
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#include "ehci-core.h"
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@@ -39,6 +40,11 @@
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int ehci_hcd_init(void)
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int ehci_hcd_init(void)
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{
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{
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struct usb_ehci *ehci;
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struct usb_ehci *ehci;
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+ char usb_phy[5];
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+ const char *phy_type = NULL;
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+ size_t len;
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+
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+ usb_phy[0] = '\0';
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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@@ -52,10 +58,37 @@ int ehci_hcd_init(void)
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out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
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out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
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/* Init phy */
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/* Init phy */
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- if (!strcmp(getenv("usb_phy_type"), "utmi"))
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- out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
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+ if (hwconfig_sub("usb1", "phy_type"))
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+ phy_type = hwconfig_subarg("usb1", "phy_type", &len);
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else
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else
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+ phy_type = getenv("usb_phy_type");
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+
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+ if (!phy_type) {
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+#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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+ /* if none specified assume internal UTMI */
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+ strcpy(usb_phy, "utmi");
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+ phy_type = usb_phy;
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+#else
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+ printf("WARNING: USB phy type not defined !!\n");
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+ return -1;
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+#endif
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+ }
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+
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+ if (!strcmp(phy_type, "utmi")) {
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+#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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+ setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
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+ setbits_be32(&ehci->control, UTMI_PHY_EN);
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+ udelay(1000); /* delay required for PHY Clk to appear */
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+#endif
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+ out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
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+ } else {
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+#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
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+ clrbits_be32(&ehci->control, UTMI_PHY_EN);
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+ setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
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+ udelay(1000); /* delay required for PHY Clk to appear */
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+#endif
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out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
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out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
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+ }
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/* Enable interface. */
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/* Enable interface. */
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setbits_be32(&ehci->control, USB_EN);
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setbits_be32(&ehci->control, USB_EN);
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