Coding Style cleanup

MAINTAINERS

@@ -226,8 +226,8 @@ Denis Peter <d.peter@mpl.ch>
 	PIP405			PPC4xx
 
 Daniel Poirot <dan.poirot@windriver.com>
-        sbc8240                 MPC8240
-        sbc405                  PPC405GP
+	sbc8240			MPC8240
+	sbc405			PPC405GP
 
 Stefan Roese <stefan.roese@esd-electronics.com>
 
@@ -387,7 +387,7 @@ Rishi Bhattacharya <rishi@ti.com>
 	omap5912osk		ARM926EJS
 
 Richard Woodruff <r-woodruff2@ti.com>
-	
+
 	omap2420h4		ARM1136EJS
 
 David Müller <d.mueller@elsoft.ch>

board/RPXlite_dw/README

@@ -38,7 +38,7 @@ make all
 To support the Platform better,I added LCD panel(NL6448BC20-08) function.
 For the convenience of debug, CONFIG_PERBOOT was supported. So you just
 perss ENTER if you want to get a serial console in boot downcounting.
-Then you can switch to LCD and serial console freely just typing 
+Then you can switch to LCD and serial console freely just typing
 'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
 
 To get a LCD support u-boot,you can do the following:
@@ -93,18 +93,18 @@ In the beginning, you could just need very simple defult environment variable se
 like[include/configs/RPXlite.h] :
 
 #define CONFIG_BOOTCOMMAND                                                      \
-        "bootp; "                                                               \
-        "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
-        "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
-        "bootm"
+	"bootp; "                                                               \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
+	"bootm"
 
-This is enough for kernel NFS test. But as debug process goes on, you would expect 
+This is enough for kernel NFS test. But as debug process goes on, you would expect
 to save some time on environment variable setting and u-boot/kernel updating.
 So the default environment variable setting would become more complicated. Just like
 the one I did in include/configs/RPXlite_DW.h.
 
 Two u-boot commands, ku and uu, should be careful to use. They were designed to update
-kernel and u-boot image file respectively. You must tftp your image to default address 
+kernel and u-boot image file respectively. You must tftp your image to default address
 '100000' and then use them correctly. Yeah, you can create your own command to do this
 job. :-) The example u-boot image updating process could be :
 

board/omap2420h4/config.mk

@@ -20,7 +20,6 @@ TEXT_BASE = 0x80e80000
 # Used with full SRAM boot.
 # This is either with a GP system or a signed boot image.
 # easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
+# Comment out CONFIG_PARTIAL_SRAM for this one.
 #
 #TEXT_BASE = 0x40280000
-

board/omap2420h4/mem.c

@@ -284,10 +284,10 @@ void gpmc_init(void)
 	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
 	sdelay(1000);
 	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
-	//__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+	/* __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); */
 	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
 	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
-	//__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	/* __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); */
 	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
 	sdelay(2000);
 
@@ -303,4 +303,3 @@ void gpmc_init(void)
 	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
 	sdelay(2000);
 }
-

board/omap2420h4/omap2420h4.c

@@ -333,11 +333,11 @@ void muxSetupI2C1(void)
 
 	/* I2C1 Clock pin configuration, PIN = M19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* I2C1 Data pin configuration, PIN = L15 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* Pull-up required on data line */
 	/* external pull-up already present. */
@@ -379,91 +379,91 @@ void muxSetupLCD(void)
 
 	/* LCD_D0 pin configuration, PIN = Y7  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D1 pin configuration, PIN = P10 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D2 pin configuration, PIN = V8  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D3 pin configuration, PIN = Y8  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D4 pin configuration, PIN = W8  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D5 pin configuration, PIN = R10 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D6 pin configuration, PIN = Y9  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D7 pin configuration, PIN = V9  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D8 pin configuration, PIN = W9  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D9 pin configuration, PIN = P11 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D10 pin configuration, PIN = V10 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D11 pin configuration, PIN = Y10 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D12 pin configuration, PIN = W10 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D13 pin configuration, PIN = R11 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D14 pin configuration, PIN = V11 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D15 pin configuration, PIN = W11 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D16 pin configuration, PIN = P12 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_D17 pin configuration, PIN = R12 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_PCLK pin configuration,   PIN = W6   */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_VSYNC pin configuration,  PIN = V7  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_HSYNC pin configuration,  PIN = Y6  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* LCD_ACBIAS pin configuration, PIN = W7 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 }
 
 /****************************************
@@ -477,63 +477,63 @@ void muxSetupCamera(void)
 	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 	/* CAM_RST is connected through the I2C IO expander.*/
 	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
-	/* *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled   */
+	/* *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled   */
 
 	/* CAMERA_XCLK  pin configuration, PIN = U3 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_LCLK  pin configuration, PIN = V5 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
-	*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_VSYNC pin configuration, PIN = U2 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_HSYNC pin configuration, PIN = T3 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT0 pin configuration, PIN = T4 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT1 pin configuration, PIN = V2 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT2 pin configuration, PIN = V3 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT3 pin configuration, PIN = U4 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT4 pin configuration, PIN = W2 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT5 pin configuration, PIN = V4 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT6 pin configuration, PIN = W3 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* CAMERA_DAT9 pin configuration, PIN = V6 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 }
 
 /****************************************
@@ -546,70 +546,70 @@ void muxSetupMMCSD(void)
 
 	/* SDMMC_CLKI pin configuration,  PIN = H15 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_CLKO pin configuration,  PIN = G19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_CMD pin configuration,   PIN = H18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
-	// External pull-ups are present.
-	// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 
 	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
-	// External pull-ups are present.
-	// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 
 	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
-	// External pull-ups are present.
-	// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 
 	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
-	// External pull-ups are present.
-	// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 
 	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
-	// External pull-ups are present.
-	// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 
 	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SDMMC_CDIR pin configuration,  PIN = G18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 	/* MMC_CD for 2422IP=K1 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
-				   *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 
 	/* MMC_WP pin configuration,      PIN = B4  */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
-				   *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 }
 
 /******************************************
@@ -622,23 +622,23 @@ void muxSetupTouchScreen(void)
 
 	/* SPI1_CLK pin configuration,  PIN = U18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SPI1_MOSI pin configuration, PIN = V20 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SPI1_MISO pin configuration, PIN = T18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* SPI1_nCS0 pin configuration, PIN = U19 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 
 	/* PEN_IRQ pin configuration,   PIN = P20 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
-				   *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 }
 
 /****************************************
@@ -651,7 +651,7 @@ void muxSetupHDQ(void)
 
 	/* HDQ_SIO pin configuration,  PIN = N18 */
 	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
-				   *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 }
 
 /***************************************************************
@@ -830,5 +830,3 @@ void update_mux(u32 btype,u32 mtype)
 		}
 	}
 }
-
-

board/omap2420h4/platform.S

@@ -15,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -41,109 +41,109 @@ _TEXT_BASE:
  *************************************************************************/
 .global cpy_clk_code
  cpy_clk_code:
-        /* Copy DPLL code into SRAM */ 
-        adr     r0, go_to_speed         /* get addr of clock setting code */
-        mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
-        mov     r1, r1                  /* r1 <- dest address (passed in) */
-        add     r2, r2, r0              /* r2 <- source end address */
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
 next2:
-        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-        cmp     r0, r2                  /* until source end address [r2]    */
-        bne     next2
-	mov	pc, lr                  /* back to caller */
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next2
+	mov	pc, lr			/* back to caller */
 
-/* **************************************************************************** 
+/* ****************************************************************************
  *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- *               -executed from SRAM.
+ *		 -executed from SRAM.
  *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
  *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
  *  R2 = dpll value
  *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/    
+ ******************************************************************************/
 .global go_to_speed
  go_to_speed:
-        sub     sp, sp, #0x4 /* get some stack space */
-        str     r4, [sp]     /* save r4's value */
-
-        /* move into fast relock bypass */
-        ldr     r8, pll_ctl_add
-        mov     r4, #0x2
-        str     r4, [r8]
-        ldr     r4, pll_stat
+	sub	sp, sp, #0x4 /* get some stack space */
+	str	r4, [sp]     /* save r4's value */
+
+	/* move into fast relock bypass */
+	ldr	r8, pll_ctl_add
+	mov	r4, #0x2
+	str	r4, [r8]
+	ldr	r4, pll_stat
 block:
-        ldr     r8, [r4]	/* wait for bypass to take effect */
-        and     r8, r8, #0x3
-        cmp     r8, #0x1
-        bne     block
+	ldr	r8, [r4]	/* wait for bypass to take effect */
+	and	r8, r8, #0x3
+	cmp	r8, #0x1
+	bne	block
 
 	/* set new dpll dividers _after_ in bypass */
-	ldr     r4, pll_div_add
-	ldr     r8, pll_div_val
-        str     r8, [r4]
-    
-        /* now prepare GPMC (flash) for new dpll speed */
+	ldr	r4, pll_div_add
+	ldr	r8, pll_div_val
+	str	r8, [r4]
+
+	/* now prepare GPMC (flash) for new dpll speed */
 	/* flash needs to be stable when we jump back to it */
-        ldr     r4, cfg3_0_addr
-        ldr     r8, cfg3_0_val
-        str     r8, [r4]
-        ldr     r4, cfg4_0_addr
-        ldr     r8, cfg4_0_val
-        str     r8, [r4]
-        ldr     r4, cfg1_0_addr
-        ldr     r8, [r4]
-        orr     r8, r8, #0x3     /* up gpmc divider */
-        str     r8, [r4]
-
-	/* setup to 2x loop though code.  The first loop pre-loads the 
-         * icache, the 2nd commits the prcm config, and locks the dpll
-         */
-        mov     r4, #0x1000      /* spin spin spin */
-        mov     r8, #0x4         /* first pass condition & set registers */
-        cmp     r8, #0x4
+	ldr	r4, cfg3_0_addr
+	ldr	r8, cfg3_0_val
+	str	r8, [r4]
+	ldr	r4, cfg4_0_addr
+	ldr	r8, cfg4_0_val
+	str	r8, [r4]
+	ldr	r4, cfg1_0_addr
+	ldr	r8, [r4]
+	orr	r8, r8, #0x3	 /* up gpmc divider */
+	str	r8, [r4]
+
+	/* setup to 2x loop though code.  The first loop pre-loads the
+	 * icache, the 2nd commits the prcm config, and locks the dpll
+	 */
+	mov	r4, #0x1000	 /* spin spin spin */
+	mov	r8, #0x4	 /* first pass condition & set registers */
+	cmp	r8, #0x4
 2:
-        ldrne   r8, [r3]         /* DPLL lock check */
-        and     r8, r8, #0x7
-        cmp     r8, #0x2
-        beq     4f
+	ldrne	r8, [r3]	 /* DPLL lock check */
+	and	r8, r8, #0x7
+	cmp	r8, #0x2
+	beq	4f
 3:
-        subeq   r8, r8, #0x1
-        streq   r8, [r0]         /* commit dividers (2nd time) */
-        nop
+	subeq	r8, r8, #0x1
+	streq	r8, [r0]	 /* commit dividers (2nd time) */
+	nop
 lloop1:
-        sub     r4, r4, #0x1    /* Loop currently necessary else bad jumps */
-        nop
-        cmp     r4, #0x0
-        bne     lloop1
-        mov     r4, #0x40000
-        cmp     r8, #0x1
-        nop
-        streq   r2, [r1]        /* lock dpll (2nd time) */
-        nop
+	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop1
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	streq	r2, [r1]	/* lock dpll (2nd time) */
+	nop
 lloop2:
-        sub     r4, r4, #0x1    /* loop currently necessary else bad jumps */
-        nop
-        cmp     r4, #0x0
-        bne     lloop2
-        mov     r4, #0x40000
-        cmp     r8, #0x1
-        nop
-        ldreq   r8, [r3]         /* get lock condition for dpll */
-        cmp     r8, #0x4         /* first time though? */
-        bne     2b
-        moveq   r8, #0x2         /* set to dpll check condition. */
-        beq     3b               /* if condition not true branch */
-4:  
-        ldr     r4, [sp]
-        add     sp, sp, #0x4     /* return stack space */
-        mov     pc, lr           /* back to caller, locked */        
+	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop2
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	ldreq	r8, [r3]	 /* get lock condition for dpll */
+	cmp	r8, #0x4	 /* first time though? */
+	bne	2b
+	moveq	r8, #0x2	 /* set to dpll check condition. */
+	beq	3b		 /* if condition not true branch */
+4:
+	ldr	r4, [sp]
+	add	sp, sp, #0x4	 /* return stack space */
+	mov	pc, lr		 /* back to caller, locked */
 
 _go_to_speed: .word go_to_speed
 
 /* these constants need to be close for PIC code */
 cfg3_0_addr:
     .word  GPMC_CONFIG3_0
-cfg3_0_val: 
+cfg3_0_val:
     .word  H4_24XX_GPMC_CONFIG3_0
 cfg4_0_addr:
     .word  GPMC_CONFIG4_0
@@ -156,10 +156,10 @@ pll_ctl_add:
 pll_stat:
     .word CM_IDLEST_CKGEN
 pll_div_add:
-    .word CM_CLKSEL1_PLL 
+    .word CM_CLKSEL1_PLL
 pll_div_val:
     .word DPLL_VAL	/* DPLL setting (300MHz default) */
-#endif            
+#endif
 
 .globl platformsetup
 platformsetup:
@@ -175,23 +175,23 @@ platformsetup:
 	ldr	r0,	REG_SDRC_SHARING
 	ldr	r1,	VAL_SDRC_SHARING
 	str	r1,	[r0]
-       	ldr	r0,	REG_SDRC_RFR_CTRL_0
+	ldr	r0,	REG_SDRC_RFR_CTRL_0
 	ldr	r1,	VAL_SDRC_RFR_CTRL_0
 	str	r1,	[r0]
 
        /* little delay after init */
-       mov r2, #0x1800                        
-1:       
-        subs r2, r2, #0x1
-        bne 1b
+       mov r2, #0x1800
+1:
+	subs r2, r2, #0x1
+	bne 1b
 #endif
 #ifdef CONFIG_PARTIAL_SRAM
 	ldr	sp,	SRAM_STACK
-        str     ip,	[sp]    /* stash old link register */
+	str	ip,	[sp]	/* stash old link register */
 	mov	ip,	lr	/* save link reg across call */
-        mov     r0,     r3      /* pass skip info to s_init */
-        bl      s_init          /* go setup pll,mux,memory */
-        ldr     ip,	[sp]    /* restore save ip */
+	mov	r0,	r3	/* pass skip info to s_init */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
 	mov	lr,	ip	/* restore link reg */
 #endif
 	/* map interrupt controller */
@@ -219,7 +219,7 @@ REG_SDRC_MCFG_0:
 REG_SDRC_MR_0:
 	.word SDRC_MR_0
 REG_SDRC_RFR_CTRL_0:
-        .word SDRC_RFR_CTRL
+	.word SDRC_RFR_CTRL
 VAL_SDRC_SHARING:
 	.word VAL_H4_SDRC_SHARING
 VAL_SDRC_MCFG_0:
@@ -227,11 +227,5 @@ VAL_SDRC_MCFG_0:
 VAL_SDRC_MR_0:
 	.word VAL_H4_SDRC_MR_0
 VAL_SDRC_RFR_CTRL_0:
-        .word VAL_H4_SDRC_RFR_CTRL_0
+	.word VAL_H4_SDRC_RFR_CTRL_0
 #endif
-
-
-
-
-
-

board/omap2420h4/u-boot.lds

@@ -1,6 +1,6 @@
 /*
- * January 2004 - Changed to support H4 device 
- * Copyright (c) 2004 Texas Instruments 
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
  *
  * (C) Copyright 2002
  * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
@@ -15,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -32,7 +32,7 @@ SECTIONS
 	. = 0x00000000;
 
 	. = ALIGN(4);
-	.text      :
+	.text	   :
 	{
 	  cpu/arm1136/start.o	(.text)
 	  *(.text)

cpu/arm1136/cpu.c

@@ -124,8 +124,8 @@ int cleanup_before_linux (void)
 
 	/* flush I/D-cache */
 	i = 0;
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  // invalidate both caches and flush btb
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); // mem barrier to sync things
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 	return(0);
 }
 

cpu/arm1136/interrupts.c

@@ -1,14 +1,11 @@
 /*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
+ * (C) Copyright 2004
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
  *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
  *
  * (C) Copyright 2002

cpu/arm1136/start.S

@@ -1,7 +1,7 @@
 /*
  *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
  *
- *  Copyright (c) 2004  Texas Instruments <r-woodruff2@ti.com>
+ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
  *
  *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
  *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
@@ -19,7 +19,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -33,7 +33,7 @@
 #include <asm/arch/omap2420.h>
 
 .globl _start
-_start:	b       reset
+_start: b	reset
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -42,14 +42,14 @@ _start:	b       reset
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
-_undefined_instruction:	.word undefined_instruction
+_undefined_instruction: .word undefined_instruction
 _software_interrupt:	.word software_interrupt
 _prefetch_abort:	.word prefetch_abort
 _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
-_pad:                   .word 0x12345678 /* now 16*4=64 */ 
+_pad:			.word 0x12345678 /* now 16*4=64 */
 .global _end_vect
 _end_vect:
 
@@ -111,22 +111,22 @@ reset:
 	msr	cpsr,r0
 
 #ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */ 
-        adr     r0, _start              /* r0 <- current position of code   */
-        mov     r2, #64                 /* r2 <- size to copy  */
-        add     r2, r0, r2              /* r2 <- source end address         */
-        mov     r1, #SRAM_OFFSET0         /* build vect addr */
-        mov     r3, #SRAM_OFFSET1
-        add     r1, r1, r3
-        mov     r3, #SRAM_OFFSET2
-        add     r1, r1, r3
+       /* Copy vectors to mask ROM indirect addr */
+	adr	r0, _start		/* r0 <- current position of code   */
+	mov	r2, #64			/* r2 <- size to copy  */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
 next:
-        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
-        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
-        cmp     r0, r2                  /* until source end address [r2]    */
-        bne     next                    /* loop until equal */
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next			/* loop until equal */
 #ifdef CONFIG_PARTIAL_SRAM
-	bl	cpy_clk_code            /* put dpll adjust code behind vectors */
+	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
 #endif
 #endif
 	/* the mask ROM code should have PLL and others stable */
@@ -135,13 +135,13 @@ next:
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
+	cmp	r0, r1			/* don't reloc during debug	    */
+	beq	stack_setup
 
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
+	sub	r2, r3, r2		/* r2 <- size of armboot	    */
+	add	r2, r0, r2		/* r2 <- source end address	    */
 
 copy_loop:
 	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
@@ -152,26 +152,26 @@ copy_loop:
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+	sub	r0, r0, #CFG_MALLOC_LEN /* malloc area			    */
+	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo			    */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 
 clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
+	ldr	r0, _bss_start		/* find start of bss segment	    */
+	ldr	r1, _bss_end		/* stop here			    */
+	mov	r2, #0x00000000		/* clear			    */
 
-clbss_l:str	r2, [r0]		/* clear loop...                    */
+clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
 
 	ldr	pc, _start_armboot
 
-_start_armboot:	.word start_armboot
+_start_armboot: .word start_armboot
 
 
 /*
@@ -205,18 +205,18 @@ cpu_init_crit:
 	mcr	p15, 0, r0, c1, c0, 0
 
 	/*
-         * Jump to board specific initialization... The Mask ROM will have already initialized
-         * basic memory.  Go here to bump up clock rate and handle wake up conditions.
+	 * Jump to board specific initialization... The Mask ROM will have already initialized
+	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
 	 */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* pass on info about skipping some init portions */
-        moveq   r0,#0x1                 /* flag to skip prcm and sdrc setup */
-        movne   r0,#0x0                 
-	mov	ip, lr          /* persevere link reg across call */
-	bl	platformsetup   /* go setup pll,mux,memory */
-	mov	lr, ip          /* restore link */
-	mov	pc, lr          /* back to my caller */
+	cmp	r0, r1			/* pass on info about skipping some init portions */
+	moveq	r0,#0x1			/* flag to skip prcm and sdrc setup */
+	movne	r0,#0x0
+	mov	ip, lr		/* persevere link reg across call */
+	bl	platformsetup	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
 /*
  *************************************************************************
  *
@@ -258,30 +258,30 @@ cpu_init_crit:
  */
 
 	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
 	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
 
 	ldr	r2, _armboot_start
 	sub	r2, r2, #(CFG_MALLOC_LEN)
-	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-	ldmia	r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
+	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
 	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
 
 	add	r5, sp, #S_SP
 	mov	r1, lr
-	stmia	r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp                          @ save current stack into r0 (param register)
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0 (param register)
 	.endm
 
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
+	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 
@@ -295,31 +295,31 @@ cpu_init_crit:
 
 	.macro get_bad_stack
 	ldr	r13, _armboot_start		@ setup our mode stack (enter in banked mode)
-	sub	r13, r13, #(CFG_MALLOC_LEN)     @ move past malloc pool
+	sub	r13, r13, #(CFG_MALLOC_LEN)	@ move past malloc pool
 	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
 
 	str	lr, [r13]			@ save caller lr in position 0 of saved stack
-	mrs	lr, spsr                        @ get the spsr
-	str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
 
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13
-	msr	spsr, r13                       @ switch modes, make sure moves will execute
-	mov	lr, pc                          @ capture return pc
-	movs	pc, lr                          @ jump to next instruction & switch modes.
+	msr	spsr, r13			@ switch modes, make sure moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction & switch modes.
 	.endm
 
 	.macro get_bad_stack_swi
-        sub     r13, r13, #4                    @ space on current stack for scratch reg.
-        str     r0, [r13]                       @ save R0's value.
+	sub	r13, r13, #4			@ space on current stack for scratch reg.
+	str	r0, [r13]			@ save R0's value.
 	ldr	r0, _armboot_start		@ get data regions start
-	sub	r0, r0, #(CFG_MALLOC_LEN)       @ move past malloc pool
-	sub	r0, r0, #(CFG_GBL_DATA_SIZE+8)  @ move past gbl and a couple spots for abort stack
+	sub	r0, r0, #(CFG_MALLOC_LEN)	@ move past malloc pool
+	sub	r0, r0, #(CFG_GBL_DATA_SIZE+8)	@ move past gbl and a couple spots for abort stack
 	str	lr, [r0]			@ save caller lr in position 0 of saved stack
-	mrs	r0, spsr                        @ get the spsr
-	str     lr, [r0, #4]                    @ save spsr in position 1 of saved stack
-        ldr     r0, [r13]                       @ restore r0
-        add     r13, r13, #4                    @ pop stack entry
+	mrs	r0, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
 	.endm
 
 	.macro get_irq_stack			@ setup IRQ stack
@@ -333,35 +333,35 @@ cpu_init_crit:
 /*
  * exception handlers
  */
-	.align  5
+	.align	5
 undefined_instruction:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_undefined_instruction
+	bl	do_undefined_instruction
 
 	.align	5
 software_interrupt:
 	get_bad_stack_swi
 	bad_save_user_regs
-	bl 	do_software_interrupt
+	bl	do_software_interrupt
 
 	.align	5
 prefetch_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_prefetch_abort
+	bl	do_prefetch_abort
 
 	.align	5
 data_abort:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_data_abort
+	bl	do_data_abort
 
 	.align	5
 not_used:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_not_used
+	bl	do_not_used
 
 #ifdef CONFIG_USE_IRQ
 
@@ -369,7 +369,7 @@ not_used:
 irq:
 	get_irq_stack
 	irq_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 	irq_restore_user_regs
 
 	.align	5
@@ -377,7 +377,7 @@ fiq:
 	get_fiq_stack
 	/* someone ought to write a more effiction fiq_save_user_regs */
 	irq_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 	irq_restore_user_regs
 
 #else
@@ -386,13 +386,13 @@ fiq:
 irq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_irq
+	bl	do_irq
 
 	.align	5
 fiq:
 	get_bad_stack
 	bad_save_user_regs
-	bl 	do_fiq
+	bl	do_fiq
 
 #endif
 	.align 5
@@ -404,9 +404,9 @@ arm1136_cache_flush:
 	.align	5
 .globl reset_cpu
 reset_cpu:
-	ldr	r1, rstctl      /* get addr for global reset reg */
-	mov     r3, #0x3	/* full reset pll+mpu */
-	str	r3, [r1]        /* force reset */
+	ldr	r1, rstctl	/* get addr for global reset reg */
+	mov	r3, #0x3	/* full reset pll+mpu */
+	str	r3, [r1]	/* force reset */
 	mov	r0, r0
 _loop_forever:
 	b	_loop_forever

drivers/8390.h

@@ -92,8 +92,6 @@ are GPL, so this is, of course, GPL.
 #define ENDCFG_AUTO_INIT   0x10        /* Auto-init to remove packets from ring */
 #define ENDCFG_FIFO		0x40	/* 8 bytes */
 
-
-
 /* Page 1 register offsets. */
 #define EN1_PHYS   EI_SHIFT(0x01)	/* This board's physical enet addr RD WR */
 #define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */

drivers/omap24xx_i2c.c

@@ -44,8 +44,8 @@ void i2c_init (int speed, int slaveadd)
 
 	/* 12Mhz I2C module clock */
 	outw (0, I2C_PSC);
-        speed = speed/1000;                 /* 100 or 400 */
-        scl = ((12000/(speed*2)) - 7);  /* use 7 when PSC = 0 */
+	speed = speed/1000;		    /* 100 or 400 */
+	scl = ((12000/(speed*2)) - 7);	/* use 7 when PSC = 0 */
 	outw (scl, I2C_SCLL);
 	outw (scl, I2C_SCLH);
 	/* own address */
@@ -174,10 +174,10 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 
 void flush_fifo(void)
 {	u16 stat;
-	
-	/* note: if you try and read data when its not there or ready 
-         * you get a bus error
-         */
+
+	/* note: if you try and read data when its not there or ready
+	 * you get a bus error
+	 */
 	while(1){
 		stat = inw(I2C_STAT);
 		if(stat == I2C_STAT_RRDY){
@@ -210,11 +210,11 @@ int i2c_probe (uchar chip)
 	udelay (50000);
 
 	if (!(inw (I2C_STAT) & I2C_STAT_NACK)) {
-		res = 0;      /* success case */ 
+		res = 0;      /* success case */
 		flush_fifo();
 		outw(0xFFFF, I2C_STAT);
 	} else {
-		outw(0xFFFF, I2C_STAT);  /* failue, clear sources*/
+		outw(0xFFFF, I2C_STAT);	 /* failue, clear sources*/
 		outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
 		udelay(20000);
 		wait_for_bb ();
@@ -280,7 +280,7 @@ static void wait_for_bb (void)
 	int timeout = 10;
 	u16 stat;
 
-	outw(0xFFFF, I2C_STAT);  /* clear current interruts...*/
+	outw(0xFFFF, I2C_STAT);	 /* clear current interruts...*/
 	while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
 		outw (stat, I2C_STAT);
 		udelay (50000);
@@ -290,7 +290,7 @@ static void wait_for_bb (void)
 		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
 			inw (I2C_STAT));
 	}
-	outw(0xFFFF, I2C_STAT);  /* clear delayed stuff*/
+	outw(0xFFFF, I2C_STAT);	 /* clear delayed stuff*/
 }
 
 static u16 wait_for_pin (void)
@@ -309,7 +309,7 @@ static u16 wait_for_pin (void)
 	if (timeout <= 0) {
 		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
 			inw (I2C_STAT));
-			outw(0xFFFF, I2C_STAT);	
+			outw(0xFFFF, I2C_STAT);
 }
 	return status;
 }

include/asm-arm/arch-arm1136/bits.h

@@ -46,4 +46,3 @@
 #define BIT31 (1<<31)
 
 #endif
-

include/asm-arm/arch-arm1136/clocks.h

@@ -76,4 +76,3 @@
 #define LDELAY           12000000
 
 #endif
-

include/asm-arm/arch-arm1136/omap2420.h

@@ -197,4 +197,3 @@
 #endif  /* endif CONFIG_2420H4 */
 
 #endif
-

include/asm-arm/arch-arm1136/rev.h

@@ -56,4 +56,3 @@ typedef	struct	h4_system_data {
 #define CPU_2420_ES2    2
 
 #endif
-

include/asm-arm/arch-arm1136/sizes.h

@@ -47,4 +47,3 @@
 #define SZ_2G				0x80000000
 
 #endif	/* __sizes_h */
-

include/asm-arm/arch-arm1136/sys_info.h

@@ -75,4 +75,3 @@ typedef struct  h4_system_data {
 #define I2C_MENELAUS 0x72	/* i2c id for companion chip */
 
 #endif
-

include/asm-arm/arch-arm1136/sys_proto.h

@@ -45,4 +45,3 @@ u32 get_board_type(void);
 void display_board_info(u32);
 void update_mux(u32,u32);
 #endif
-

include/configs/RPXlite_DW.h

@@ -108,7 +108,7 @@
 	"lcd=setenv stdout lcd;setenv stdin lcd\0"			\
 	"ser=setenv stdout serial;setenv stdin serial\0"		\
 	"verify=no"
-	
+
 =======
 	"kernel_addr=ff080000\0"					\
 	"ramdisk_addr=ff200000\0"					\
@@ -209,7 +209,7 @@
 
 <<<<<<< RPXlite_DW.h
 #define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
-	
+
 =======
 #define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
 

include/configs/omap2420h4.h

@@ -35,10 +35,10 @@
 #define CONFIG_OMAP              1    /* in a TI OMAP core */
 #define CONFIG_OMAP2420	         1    /* which is in a 2420 */
 #define CONFIG_OMAP2420H4        1    /* and on a H4 board */
-//#define CONFIG_APTIX           1    /* define if on APTIX test chip */
-//#define CONFIG_VIRTIO          1    /* Using Virtio simulator */
+/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
+/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
 
-#define PRCM_CONFIG_II           1    
+#define PRCM_CONFIG_II           1
 #define CONFIG_PARTIAL_SRAM      1
 
 #include <asm/arch/omap2420.h>        /* get chip and board defs */
@@ -70,7 +70,7 @@
 /*
  * Hardware drivers
  */
- 
+
 /*
  * SMC91c96 Etherent
  */
@@ -114,8 +114,8 @@
 
 #define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C)
 
-// I'd like to get to these. Snap kernel loads if we make MMC go //
-  // #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C)
+/* I'd like to get to these. Snap kernel loads if we make MMC go */
+  /* #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
 
 #define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT