intel_pm.c 155 KB

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  1. /*
  2. * Copyright © 2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eugeni Dodonov <eugeni.dodonov@intel.com>
  25. *
  26. */
  27. #include <linux/cpufreq.h>
  28. #include "i915_drv.h"
  29. #include "intel_drv.h"
  30. #include "../../../platform/x86/intel_ips.h"
  31. #include <linux/module.h>
  32. #define FORCEWAKE_ACK_TIMEOUT_MS 2
  33. /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  34. * framebuffer contents in-memory, aiming at reducing the required bandwidth
  35. * during in-memory transfers and, therefore, reduce the power packet.
  36. *
  37. * The benefits of FBC are mostly visible with solid backgrounds and
  38. * variation-less patterns.
  39. *
  40. * FBC-related functionality can be enabled by the means of the
  41. * i915.i915_enable_fbc parameter
  42. */
  43. static bool intel_crtc_active(struct drm_crtc *crtc)
  44. {
  45. /* Be paranoid as we can arrive here with only partial
  46. * state retrieved from the hardware during setup.
  47. */
  48. return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  49. }
  50. static void i8xx_disable_fbc(struct drm_device *dev)
  51. {
  52. struct drm_i915_private *dev_priv = dev->dev_private;
  53. u32 fbc_ctl;
  54. /* Disable compression */
  55. fbc_ctl = I915_READ(FBC_CONTROL);
  56. if ((fbc_ctl & FBC_CTL_EN) == 0)
  57. return;
  58. fbc_ctl &= ~FBC_CTL_EN;
  59. I915_WRITE(FBC_CONTROL, fbc_ctl);
  60. /* Wait for compressing bit to clear */
  61. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  62. DRM_DEBUG_KMS("FBC idle timed out\n");
  63. return;
  64. }
  65. DRM_DEBUG_KMS("disabled FBC\n");
  66. }
  67. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  68. {
  69. struct drm_device *dev = crtc->dev;
  70. struct drm_i915_private *dev_priv = dev->dev_private;
  71. struct drm_framebuffer *fb = crtc->fb;
  72. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  73. struct drm_i915_gem_object *obj = intel_fb->obj;
  74. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  75. int cfb_pitch;
  76. int plane, i;
  77. u32 fbc_ctl, fbc_ctl2;
  78. cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  79. if (fb->pitches[0] < cfb_pitch)
  80. cfb_pitch = fb->pitches[0];
  81. /* FBC_CTL wants 64B units */
  82. cfb_pitch = (cfb_pitch / 64) - 1;
  83. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  84. /* Clear old tags */
  85. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  86. I915_WRITE(FBC_TAG + (i * 4), 0);
  87. /* Set it up... */
  88. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  89. fbc_ctl2 |= plane;
  90. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  91. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  92. /* enable it... */
  93. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  94. if (IS_I945GM(dev))
  95. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  96. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  97. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  98. fbc_ctl |= obj->fence_reg;
  99. I915_WRITE(FBC_CONTROL, fbc_ctl);
  100. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
  101. cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
  102. }
  103. static bool i8xx_fbc_enabled(struct drm_device *dev)
  104. {
  105. struct drm_i915_private *dev_priv = dev->dev_private;
  106. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  107. }
  108. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  109. {
  110. struct drm_device *dev = crtc->dev;
  111. struct drm_i915_private *dev_priv = dev->dev_private;
  112. struct drm_framebuffer *fb = crtc->fb;
  113. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  114. struct drm_i915_gem_object *obj = intel_fb->obj;
  115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  116. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  117. unsigned long stall_watermark = 200;
  118. u32 dpfc_ctl;
  119. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  120. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  121. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  122. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  123. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  124. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  125. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  126. /* enable it... */
  127. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  128. DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
  129. }
  130. static void g4x_disable_fbc(struct drm_device *dev)
  131. {
  132. struct drm_i915_private *dev_priv = dev->dev_private;
  133. u32 dpfc_ctl;
  134. /* Disable compression */
  135. dpfc_ctl = I915_READ(DPFC_CONTROL);
  136. if (dpfc_ctl & DPFC_CTL_EN) {
  137. dpfc_ctl &= ~DPFC_CTL_EN;
  138. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  139. DRM_DEBUG_KMS("disabled FBC\n");
  140. }
  141. }
  142. static bool g4x_fbc_enabled(struct drm_device *dev)
  143. {
  144. struct drm_i915_private *dev_priv = dev->dev_private;
  145. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  146. }
  147. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  148. {
  149. struct drm_i915_private *dev_priv = dev->dev_private;
  150. u32 blt_ecoskpd;
  151. /* Make sure blitter notifies FBC of writes */
  152. gen6_gt_force_wake_get(dev_priv);
  153. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  154. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  155. GEN6_BLITTER_LOCK_SHIFT;
  156. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  157. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  158. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  159. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  160. GEN6_BLITTER_LOCK_SHIFT);
  161. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  162. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  163. gen6_gt_force_wake_put(dev_priv);
  164. }
  165. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  166. {
  167. struct drm_device *dev = crtc->dev;
  168. struct drm_i915_private *dev_priv = dev->dev_private;
  169. struct drm_framebuffer *fb = crtc->fb;
  170. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  171. struct drm_i915_gem_object *obj = intel_fb->obj;
  172. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  173. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  174. unsigned long stall_watermark = 200;
  175. u32 dpfc_ctl;
  176. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  177. dpfc_ctl &= DPFC_RESERVED;
  178. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  179. /* Set persistent mode for front-buffer rendering, ala X. */
  180. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  181. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  182. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  183. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  184. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  185. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  186. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  187. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  188. /* enable it... */
  189. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  190. if (IS_GEN6(dev)) {
  191. I915_WRITE(SNB_DPFC_CTL_SA,
  192. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  193. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  194. sandybridge_blit_fbc_update(dev);
  195. }
  196. DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
  197. }
  198. static void ironlake_disable_fbc(struct drm_device *dev)
  199. {
  200. struct drm_i915_private *dev_priv = dev->dev_private;
  201. u32 dpfc_ctl;
  202. /* Disable compression */
  203. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  204. if (dpfc_ctl & DPFC_CTL_EN) {
  205. dpfc_ctl &= ~DPFC_CTL_EN;
  206. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  207. if (IS_IVYBRIDGE(dev))
  208. /* WaFbcDisableDpfcClockGating:ivb */
  209. I915_WRITE(ILK_DSPCLK_GATE_D,
  210. I915_READ(ILK_DSPCLK_GATE_D) &
  211. ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
  212. if (IS_HASWELL(dev))
  213. /* WaFbcDisableDpfcClockGating:hsw */
  214. I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
  215. I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
  216. ~HSW_DPFC_GATING_DISABLE);
  217. DRM_DEBUG_KMS("disabled FBC\n");
  218. }
  219. }
  220. static bool ironlake_fbc_enabled(struct drm_device *dev)
  221. {
  222. struct drm_i915_private *dev_priv = dev->dev_private;
  223. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  224. }
  225. static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  226. {
  227. struct drm_device *dev = crtc->dev;
  228. struct drm_i915_private *dev_priv = dev->dev_private;
  229. struct drm_framebuffer *fb = crtc->fb;
  230. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  231. struct drm_i915_gem_object *obj = intel_fb->obj;
  232. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  233. I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset);
  234. I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
  235. IVB_DPFC_CTL_FENCE_EN |
  236. intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
  237. if (IS_IVYBRIDGE(dev)) {
  238. /* WaFbcAsynchFlipDisableFbcQueue:ivb */
  239. I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
  240. /* WaFbcDisableDpfcClockGating:ivb */
  241. I915_WRITE(ILK_DSPCLK_GATE_D,
  242. I915_READ(ILK_DSPCLK_GATE_D) |
  243. ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
  244. } else {
  245. /* WaFbcAsynchFlipDisableFbcQueue:hsw */
  246. I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
  247. HSW_BYPASS_FBC_QUEUE);
  248. /* WaFbcDisableDpfcClockGating:hsw */
  249. I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
  250. I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
  251. HSW_DPFC_GATING_DISABLE);
  252. }
  253. I915_WRITE(SNB_DPFC_CTL_SA,
  254. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  255. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  256. sandybridge_blit_fbc_update(dev);
  257. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  258. }
  259. bool intel_fbc_enabled(struct drm_device *dev)
  260. {
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. if (!dev_priv->display.fbc_enabled)
  263. return false;
  264. return dev_priv->display.fbc_enabled(dev);
  265. }
  266. static void intel_fbc_work_fn(struct work_struct *__work)
  267. {
  268. struct intel_fbc_work *work =
  269. container_of(to_delayed_work(__work),
  270. struct intel_fbc_work, work);
  271. struct drm_device *dev = work->crtc->dev;
  272. struct drm_i915_private *dev_priv = dev->dev_private;
  273. mutex_lock(&dev->struct_mutex);
  274. if (work == dev_priv->fbc_work) {
  275. /* Double check that we haven't switched fb without cancelling
  276. * the prior work.
  277. */
  278. if (work->crtc->fb == work->fb) {
  279. dev_priv->display.enable_fbc(work->crtc,
  280. work->interval);
  281. dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  282. dev_priv->cfb_fb = work->crtc->fb->base.id;
  283. dev_priv->cfb_y = work->crtc->y;
  284. }
  285. dev_priv->fbc_work = NULL;
  286. }
  287. mutex_unlock(&dev->struct_mutex);
  288. kfree(work);
  289. }
  290. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  291. {
  292. if (dev_priv->fbc_work == NULL)
  293. return;
  294. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  295. /* Synchronisation is provided by struct_mutex and checking of
  296. * dev_priv->fbc_work, so we can perform the cancellation
  297. * entirely asynchronously.
  298. */
  299. if (cancel_delayed_work(&dev_priv->fbc_work->work))
  300. /* tasklet was killed before being run, clean up */
  301. kfree(dev_priv->fbc_work);
  302. /* Mark the work as no longer wanted so that if it does
  303. * wake-up (because the work was already running and waiting
  304. * for our mutex), it will discover that is no longer
  305. * necessary to run.
  306. */
  307. dev_priv->fbc_work = NULL;
  308. }
  309. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  310. {
  311. struct intel_fbc_work *work;
  312. struct drm_device *dev = crtc->dev;
  313. struct drm_i915_private *dev_priv = dev->dev_private;
  314. if (!dev_priv->display.enable_fbc)
  315. return;
  316. intel_cancel_fbc_work(dev_priv);
  317. work = kzalloc(sizeof *work, GFP_KERNEL);
  318. if (work == NULL) {
  319. dev_priv->display.enable_fbc(crtc, interval);
  320. return;
  321. }
  322. work->crtc = crtc;
  323. work->fb = crtc->fb;
  324. work->interval = interval;
  325. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  326. dev_priv->fbc_work = work;
  327. DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  328. /* Delay the actual enabling to let pageflipping cease and the
  329. * display to settle before starting the compression. Note that
  330. * this delay also serves a second purpose: it allows for a
  331. * vblank to pass after disabling the FBC before we attempt
  332. * to modify the control registers.
  333. *
  334. * A more complicated solution would involve tracking vblanks
  335. * following the termination of the page-flipping sequence
  336. * and indeed performing the enable as a co-routine and not
  337. * waiting synchronously upon the vblank.
  338. */
  339. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  340. }
  341. void intel_disable_fbc(struct drm_device *dev)
  342. {
  343. struct drm_i915_private *dev_priv = dev->dev_private;
  344. intel_cancel_fbc_work(dev_priv);
  345. if (!dev_priv->display.disable_fbc)
  346. return;
  347. dev_priv->display.disable_fbc(dev);
  348. dev_priv->cfb_plane = -1;
  349. }
  350. /**
  351. * intel_update_fbc - enable/disable FBC as needed
  352. * @dev: the drm_device
  353. *
  354. * Set up the framebuffer compression hardware at mode set time. We
  355. * enable it if possible:
  356. * - plane A only (on pre-965)
  357. * - no pixel mulitply/line duplication
  358. * - no alpha buffer discard
  359. * - no dual wide
  360. * - framebuffer <= max_hdisplay in width, max_vdisplay in height
  361. *
  362. * We can't assume that any compression will take place (worst case),
  363. * so the compressed buffer has to be the same size as the uncompressed
  364. * one. It also must reside (along with the line length buffer) in
  365. * stolen memory.
  366. *
  367. * We need to enable/disable FBC on a global basis.
  368. */
  369. void intel_update_fbc(struct drm_device *dev)
  370. {
  371. struct drm_i915_private *dev_priv = dev->dev_private;
  372. struct drm_crtc *crtc = NULL, *tmp_crtc;
  373. struct intel_crtc *intel_crtc;
  374. struct drm_framebuffer *fb;
  375. struct intel_framebuffer *intel_fb;
  376. struct drm_i915_gem_object *obj;
  377. int enable_fbc;
  378. unsigned int max_hdisplay, max_vdisplay;
  379. if (!i915_powersave)
  380. return;
  381. if (!I915_HAS_FBC(dev))
  382. return;
  383. /*
  384. * If FBC is already on, we just have to verify that we can
  385. * keep it that way...
  386. * Need to disable if:
  387. * - more than one pipe is active
  388. * - changing FBC params (stride, fence, mode)
  389. * - new fb is too large to fit in compressed buffer
  390. * - going to an unsupported config (interlace, pixel multiply, etc.)
  391. */
  392. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  393. if (intel_crtc_active(tmp_crtc) &&
  394. !to_intel_crtc(tmp_crtc)->primary_disabled) {
  395. if (crtc) {
  396. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  397. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  398. goto out_disable;
  399. }
  400. crtc = tmp_crtc;
  401. }
  402. }
  403. if (!crtc || crtc->fb == NULL) {
  404. DRM_DEBUG_KMS("no output, disabling\n");
  405. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  406. goto out_disable;
  407. }
  408. intel_crtc = to_intel_crtc(crtc);
  409. fb = crtc->fb;
  410. intel_fb = to_intel_framebuffer(fb);
  411. obj = intel_fb->obj;
  412. enable_fbc = i915_enable_fbc;
  413. if (enable_fbc < 0) {
  414. DRM_DEBUG_KMS("fbc set to per-chip default\n");
  415. enable_fbc = 1;
  416. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  417. enable_fbc = 0;
  418. }
  419. if (!enable_fbc) {
  420. DRM_DEBUG_KMS("fbc disabled per module param\n");
  421. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  422. goto out_disable;
  423. }
  424. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  425. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  426. DRM_DEBUG_KMS("mode incompatible with compression, "
  427. "disabling\n");
  428. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  429. goto out_disable;
  430. }
  431. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  432. max_hdisplay = 4096;
  433. max_vdisplay = 2048;
  434. } else {
  435. max_hdisplay = 2048;
  436. max_vdisplay = 1536;
  437. }
  438. if ((crtc->mode.hdisplay > max_hdisplay) ||
  439. (crtc->mode.vdisplay > max_vdisplay)) {
  440. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  441. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  442. goto out_disable;
  443. }
  444. if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
  445. intel_crtc->plane != 0) {
  446. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  447. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  448. goto out_disable;
  449. }
  450. /* The use of a CPU fence is mandatory in order to detect writes
  451. * by the CPU to the scanout and trigger updates to the FBC.
  452. */
  453. if (obj->tiling_mode != I915_TILING_X ||
  454. obj->fence_reg == I915_FENCE_REG_NONE) {
  455. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  456. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  457. goto out_disable;
  458. }
  459. /* If the kernel debugger is active, always disable compression */
  460. if (in_dbg_master())
  461. goto out_disable;
  462. if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
  463. DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
  464. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  465. goto out_disable;
  466. }
  467. /* If the scanout has not changed, don't modify the FBC settings.
  468. * Note that we make the fundamental assumption that the fb->obj
  469. * cannot be unpinned (and have its GTT offset and fence revoked)
  470. * without first being decoupled from the scanout and FBC disabled.
  471. */
  472. if (dev_priv->cfb_plane == intel_crtc->plane &&
  473. dev_priv->cfb_fb == fb->base.id &&
  474. dev_priv->cfb_y == crtc->y)
  475. return;
  476. if (intel_fbc_enabled(dev)) {
  477. /* We update FBC along two paths, after changing fb/crtc
  478. * configuration (modeswitching) and after page-flipping
  479. * finishes. For the latter, we know that not only did
  480. * we disable the FBC at the start of the page-flip
  481. * sequence, but also more than one vblank has passed.
  482. *
  483. * For the former case of modeswitching, it is possible
  484. * to switch between two FBC valid configurations
  485. * instantaneously so we do need to disable the FBC
  486. * before we can modify its control registers. We also
  487. * have to wait for the next vblank for that to take
  488. * effect. However, since we delay enabling FBC we can
  489. * assume that a vblank has passed since disabling and
  490. * that we can safely alter the registers in the deferred
  491. * callback.
  492. *
  493. * In the scenario that we go from a valid to invalid
  494. * and then back to valid FBC configuration we have
  495. * no strict enforcement that a vblank occurred since
  496. * disabling the FBC. However, along all current pipe
  497. * disabling paths we do need to wait for a vblank at
  498. * some point. And we wait before enabling FBC anyway.
  499. */
  500. DRM_DEBUG_KMS("disabling active FBC for update\n");
  501. intel_disable_fbc(dev);
  502. }
  503. intel_enable_fbc(crtc, 500);
  504. return;
  505. out_disable:
  506. /* Multiple disables should be harmless */
  507. if (intel_fbc_enabled(dev)) {
  508. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  509. intel_disable_fbc(dev);
  510. }
  511. i915_gem_stolen_cleanup_compression(dev);
  512. }
  513. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  514. {
  515. drm_i915_private_t *dev_priv = dev->dev_private;
  516. u32 tmp;
  517. tmp = I915_READ(CLKCFG);
  518. switch (tmp & CLKCFG_FSB_MASK) {
  519. case CLKCFG_FSB_533:
  520. dev_priv->fsb_freq = 533; /* 133*4 */
  521. break;
  522. case CLKCFG_FSB_800:
  523. dev_priv->fsb_freq = 800; /* 200*4 */
  524. break;
  525. case CLKCFG_FSB_667:
  526. dev_priv->fsb_freq = 667; /* 167*4 */
  527. break;
  528. case CLKCFG_FSB_400:
  529. dev_priv->fsb_freq = 400; /* 100*4 */
  530. break;
  531. }
  532. switch (tmp & CLKCFG_MEM_MASK) {
  533. case CLKCFG_MEM_533:
  534. dev_priv->mem_freq = 533;
  535. break;
  536. case CLKCFG_MEM_667:
  537. dev_priv->mem_freq = 667;
  538. break;
  539. case CLKCFG_MEM_800:
  540. dev_priv->mem_freq = 800;
  541. break;
  542. }
  543. /* detect pineview DDR3 setting */
  544. tmp = I915_READ(CSHRDDR3CTL);
  545. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  546. }
  547. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  548. {
  549. drm_i915_private_t *dev_priv = dev->dev_private;
  550. u16 ddrpll, csipll;
  551. ddrpll = I915_READ16(DDRMPLL1);
  552. csipll = I915_READ16(CSIPLL0);
  553. switch (ddrpll & 0xff) {
  554. case 0xc:
  555. dev_priv->mem_freq = 800;
  556. break;
  557. case 0x10:
  558. dev_priv->mem_freq = 1066;
  559. break;
  560. case 0x14:
  561. dev_priv->mem_freq = 1333;
  562. break;
  563. case 0x18:
  564. dev_priv->mem_freq = 1600;
  565. break;
  566. default:
  567. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  568. ddrpll & 0xff);
  569. dev_priv->mem_freq = 0;
  570. break;
  571. }
  572. dev_priv->ips.r_t = dev_priv->mem_freq;
  573. switch (csipll & 0x3ff) {
  574. case 0x00c:
  575. dev_priv->fsb_freq = 3200;
  576. break;
  577. case 0x00e:
  578. dev_priv->fsb_freq = 3733;
  579. break;
  580. case 0x010:
  581. dev_priv->fsb_freq = 4266;
  582. break;
  583. case 0x012:
  584. dev_priv->fsb_freq = 4800;
  585. break;
  586. case 0x014:
  587. dev_priv->fsb_freq = 5333;
  588. break;
  589. case 0x016:
  590. dev_priv->fsb_freq = 5866;
  591. break;
  592. case 0x018:
  593. dev_priv->fsb_freq = 6400;
  594. break;
  595. default:
  596. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  597. csipll & 0x3ff);
  598. dev_priv->fsb_freq = 0;
  599. break;
  600. }
  601. if (dev_priv->fsb_freq == 3200) {
  602. dev_priv->ips.c_m = 0;
  603. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  604. dev_priv->ips.c_m = 1;
  605. } else {
  606. dev_priv->ips.c_m = 2;
  607. }
  608. }
  609. static const struct cxsr_latency cxsr_latency_table[] = {
  610. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  611. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  612. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  613. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  614. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  615. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  616. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  617. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  618. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  619. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  620. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  621. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  622. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  623. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  624. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  625. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  626. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  627. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  628. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  629. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  630. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  631. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  632. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  633. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  634. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  635. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  636. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  637. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  638. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  639. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  640. };
  641. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  642. int is_ddr3,
  643. int fsb,
  644. int mem)
  645. {
  646. const struct cxsr_latency *latency;
  647. int i;
  648. if (fsb == 0 || mem == 0)
  649. return NULL;
  650. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  651. latency = &cxsr_latency_table[i];
  652. if (is_desktop == latency->is_desktop &&
  653. is_ddr3 == latency->is_ddr3 &&
  654. fsb == latency->fsb_freq && mem == latency->mem_freq)
  655. return latency;
  656. }
  657. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  658. return NULL;
  659. }
  660. static void pineview_disable_cxsr(struct drm_device *dev)
  661. {
  662. struct drm_i915_private *dev_priv = dev->dev_private;
  663. /* deactivate cxsr */
  664. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  665. }
  666. /*
  667. * Latency for FIFO fetches is dependent on several factors:
  668. * - memory configuration (speed, channels)
  669. * - chipset
  670. * - current MCH state
  671. * It can be fairly high in some situations, so here we assume a fairly
  672. * pessimal value. It's a tradeoff between extra memory fetches (if we
  673. * set this value too high, the FIFO will fetch frequently to stay full)
  674. * and power consumption (set it too low to save power and we might see
  675. * FIFO underruns and display "flicker").
  676. *
  677. * A value of 5us seems to be a good balance; safe for very low end
  678. * platforms but not overly aggressive on lower latency configs.
  679. */
  680. static const int latency_ns = 5000;
  681. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  682. {
  683. struct drm_i915_private *dev_priv = dev->dev_private;
  684. uint32_t dsparb = I915_READ(DSPARB);
  685. int size;
  686. size = dsparb & 0x7f;
  687. if (plane)
  688. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  689. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  690. plane ? "B" : "A", size);
  691. return size;
  692. }
  693. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  694. {
  695. struct drm_i915_private *dev_priv = dev->dev_private;
  696. uint32_t dsparb = I915_READ(DSPARB);
  697. int size;
  698. size = dsparb & 0x1ff;
  699. if (plane)
  700. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  701. size >>= 1; /* Convert to cachelines */
  702. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  703. plane ? "B" : "A", size);
  704. return size;
  705. }
  706. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  707. {
  708. struct drm_i915_private *dev_priv = dev->dev_private;
  709. uint32_t dsparb = I915_READ(DSPARB);
  710. int size;
  711. size = dsparb & 0x7f;
  712. size >>= 2; /* Convert to cachelines */
  713. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  714. plane ? "B" : "A",
  715. size);
  716. return size;
  717. }
  718. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  719. {
  720. struct drm_i915_private *dev_priv = dev->dev_private;
  721. uint32_t dsparb = I915_READ(DSPARB);
  722. int size;
  723. size = dsparb & 0x7f;
  724. size >>= 1; /* Convert to cachelines */
  725. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  726. plane ? "B" : "A", size);
  727. return size;
  728. }
  729. /* Pineview has different values for various configs */
  730. static const struct intel_watermark_params pineview_display_wm = {
  731. PINEVIEW_DISPLAY_FIFO,
  732. PINEVIEW_MAX_WM,
  733. PINEVIEW_DFT_WM,
  734. PINEVIEW_GUARD_WM,
  735. PINEVIEW_FIFO_LINE_SIZE
  736. };
  737. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  738. PINEVIEW_DISPLAY_FIFO,
  739. PINEVIEW_MAX_WM,
  740. PINEVIEW_DFT_HPLLOFF_WM,
  741. PINEVIEW_GUARD_WM,
  742. PINEVIEW_FIFO_LINE_SIZE
  743. };
  744. static const struct intel_watermark_params pineview_cursor_wm = {
  745. PINEVIEW_CURSOR_FIFO,
  746. PINEVIEW_CURSOR_MAX_WM,
  747. PINEVIEW_CURSOR_DFT_WM,
  748. PINEVIEW_CURSOR_GUARD_WM,
  749. PINEVIEW_FIFO_LINE_SIZE,
  750. };
  751. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  752. PINEVIEW_CURSOR_FIFO,
  753. PINEVIEW_CURSOR_MAX_WM,
  754. PINEVIEW_CURSOR_DFT_WM,
  755. PINEVIEW_CURSOR_GUARD_WM,
  756. PINEVIEW_FIFO_LINE_SIZE
  757. };
  758. static const struct intel_watermark_params g4x_wm_info = {
  759. G4X_FIFO_SIZE,
  760. G4X_MAX_WM,
  761. G4X_MAX_WM,
  762. 2,
  763. G4X_FIFO_LINE_SIZE,
  764. };
  765. static const struct intel_watermark_params g4x_cursor_wm_info = {
  766. I965_CURSOR_FIFO,
  767. I965_CURSOR_MAX_WM,
  768. I965_CURSOR_DFT_WM,
  769. 2,
  770. G4X_FIFO_LINE_SIZE,
  771. };
  772. static const struct intel_watermark_params valleyview_wm_info = {
  773. VALLEYVIEW_FIFO_SIZE,
  774. VALLEYVIEW_MAX_WM,
  775. VALLEYVIEW_MAX_WM,
  776. 2,
  777. G4X_FIFO_LINE_SIZE,
  778. };
  779. static const struct intel_watermark_params valleyview_cursor_wm_info = {
  780. I965_CURSOR_FIFO,
  781. VALLEYVIEW_CURSOR_MAX_WM,
  782. I965_CURSOR_DFT_WM,
  783. 2,
  784. G4X_FIFO_LINE_SIZE,
  785. };
  786. static const struct intel_watermark_params i965_cursor_wm_info = {
  787. I965_CURSOR_FIFO,
  788. I965_CURSOR_MAX_WM,
  789. I965_CURSOR_DFT_WM,
  790. 2,
  791. I915_FIFO_LINE_SIZE,
  792. };
  793. static const struct intel_watermark_params i945_wm_info = {
  794. I945_FIFO_SIZE,
  795. I915_MAX_WM,
  796. 1,
  797. 2,
  798. I915_FIFO_LINE_SIZE
  799. };
  800. static const struct intel_watermark_params i915_wm_info = {
  801. I915_FIFO_SIZE,
  802. I915_MAX_WM,
  803. 1,
  804. 2,
  805. I915_FIFO_LINE_SIZE
  806. };
  807. static const struct intel_watermark_params i855_wm_info = {
  808. I855GM_FIFO_SIZE,
  809. I915_MAX_WM,
  810. 1,
  811. 2,
  812. I830_FIFO_LINE_SIZE
  813. };
  814. static const struct intel_watermark_params i830_wm_info = {
  815. I830_FIFO_SIZE,
  816. I915_MAX_WM,
  817. 1,
  818. 2,
  819. I830_FIFO_LINE_SIZE
  820. };
  821. static const struct intel_watermark_params ironlake_display_wm_info = {
  822. ILK_DISPLAY_FIFO,
  823. ILK_DISPLAY_MAXWM,
  824. ILK_DISPLAY_DFTWM,
  825. 2,
  826. ILK_FIFO_LINE_SIZE
  827. };
  828. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  829. ILK_CURSOR_FIFO,
  830. ILK_CURSOR_MAXWM,
  831. ILK_CURSOR_DFTWM,
  832. 2,
  833. ILK_FIFO_LINE_SIZE
  834. };
  835. static const struct intel_watermark_params ironlake_display_srwm_info = {
  836. ILK_DISPLAY_SR_FIFO,
  837. ILK_DISPLAY_MAX_SRWM,
  838. ILK_DISPLAY_DFT_SRWM,
  839. 2,
  840. ILK_FIFO_LINE_SIZE
  841. };
  842. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  843. ILK_CURSOR_SR_FIFO,
  844. ILK_CURSOR_MAX_SRWM,
  845. ILK_CURSOR_DFT_SRWM,
  846. 2,
  847. ILK_FIFO_LINE_SIZE
  848. };
  849. static const struct intel_watermark_params sandybridge_display_wm_info = {
  850. SNB_DISPLAY_FIFO,
  851. SNB_DISPLAY_MAXWM,
  852. SNB_DISPLAY_DFTWM,
  853. 2,
  854. SNB_FIFO_LINE_SIZE
  855. };
  856. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  857. SNB_CURSOR_FIFO,
  858. SNB_CURSOR_MAXWM,
  859. SNB_CURSOR_DFTWM,
  860. 2,
  861. SNB_FIFO_LINE_SIZE
  862. };
  863. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  864. SNB_DISPLAY_SR_FIFO,
  865. SNB_DISPLAY_MAX_SRWM,
  866. SNB_DISPLAY_DFT_SRWM,
  867. 2,
  868. SNB_FIFO_LINE_SIZE
  869. };
  870. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  871. SNB_CURSOR_SR_FIFO,
  872. SNB_CURSOR_MAX_SRWM,
  873. SNB_CURSOR_DFT_SRWM,
  874. 2,
  875. SNB_FIFO_LINE_SIZE
  876. };
  877. /**
  878. * intel_calculate_wm - calculate watermark level
  879. * @clock_in_khz: pixel clock
  880. * @wm: chip FIFO params
  881. * @pixel_size: display pixel size
  882. * @latency_ns: memory latency for the platform
  883. *
  884. * Calculate the watermark level (the level at which the display plane will
  885. * start fetching from memory again). Each chip has a different display
  886. * FIFO size and allocation, so the caller needs to figure that out and pass
  887. * in the correct intel_watermark_params structure.
  888. *
  889. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  890. * on the pixel size. When it reaches the watermark level, it'll start
  891. * fetching FIFO line sized based chunks from memory until the FIFO fills
  892. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  893. * will occur, and a display engine hang could result.
  894. */
  895. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  896. const struct intel_watermark_params *wm,
  897. int fifo_size,
  898. int pixel_size,
  899. unsigned long latency_ns)
  900. {
  901. long entries_required, wm_size;
  902. /*
  903. * Note: we need to make sure we don't overflow for various clock &
  904. * latency values.
  905. * clocks go from a few thousand to several hundred thousand.
  906. * latency is usually a few thousand
  907. */
  908. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  909. 1000;
  910. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  911. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  912. wm_size = fifo_size - (entries_required + wm->guard_size);
  913. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  914. /* Don't promote wm_size to unsigned... */
  915. if (wm_size > (long)wm->max_wm)
  916. wm_size = wm->max_wm;
  917. if (wm_size <= 0)
  918. wm_size = wm->default_wm;
  919. return wm_size;
  920. }
  921. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  922. {
  923. struct drm_crtc *crtc, *enabled = NULL;
  924. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  925. if (intel_crtc_active(crtc)) {
  926. if (enabled)
  927. return NULL;
  928. enabled = crtc;
  929. }
  930. }
  931. return enabled;
  932. }
  933. static void pineview_update_wm(struct drm_device *dev)
  934. {
  935. struct drm_i915_private *dev_priv = dev->dev_private;
  936. struct drm_crtc *crtc;
  937. const struct cxsr_latency *latency;
  938. u32 reg;
  939. unsigned long wm;
  940. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  941. dev_priv->fsb_freq, dev_priv->mem_freq);
  942. if (!latency) {
  943. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  944. pineview_disable_cxsr(dev);
  945. return;
  946. }
  947. crtc = single_enabled_crtc(dev);
  948. if (crtc) {
  949. int clock = crtc->mode.clock;
  950. int pixel_size = crtc->fb->bits_per_pixel / 8;
  951. /* Display SR */
  952. wm = intel_calculate_wm(clock, &pineview_display_wm,
  953. pineview_display_wm.fifo_size,
  954. pixel_size, latency->display_sr);
  955. reg = I915_READ(DSPFW1);
  956. reg &= ~DSPFW_SR_MASK;
  957. reg |= wm << DSPFW_SR_SHIFT;
  958. I915_WRITE(DSPFW1, reg);
  959. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  960. /* cursor SR */
  961. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  962. pineview_display_wm.fifo_size,
  963. pixel_size, latency->cursor_sr);
  964. reg = I915_READ(DSPFW3);
  965. reg &= ~DSPFW_CURSOR_SR_MASK;
  966. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  967. I915_WRITE(DSPFW3, reg);
  968. /* Display HPLL off SR */
  969. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  970. pineview_display_hplloff_wm.fifo_size,
  971. pixel_size, latency->display_hpll_disable);
  972. reg = I915_READ(DSPFW3);
  973. reg &= ~DSPFW_HPLL_SR_MASK;
  974. reg |= wm & DSPFW_HPLL_SR_MASK;
  975. I915_WRITE(DSPFW3, reg);
  976. /* cursor HPLL off SR */
  977. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  978. pineview_display_hplloff_wm.fifo_size,
  979. pixel_size, latency->cursor_hpll_disable);
  980. reg = I915_READ(DSPFW3);
  981. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  982. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  983. I915_WRITE(DSPFW3, reg);
  984. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  985. /* activate cxsr */
  986. I915_WRITE(DSPFW3,
  987. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  988. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  989. } else {
  990. pineview_disable_cxsr(dev);
  991. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  992. }
  993. }
  994. static bool g4x_compute_wm0(struct drm_device *dev,
  995. int plane,
  996. const struct intel_watermark_params *display,
  997. int display_latency_ns,
  998. const struct intel_watermark_params *cursor,
  999. int cursor_latency_ns,
  1000. int *plane_wm,
  1001. int *cursor_wm)
  1002. {
  1003. struct drm_crtc *crtc;
  1004. int htotal, hdisplay, clock, pixel_size;
  1005. int line_time_us, line_count;
  1006. int entries, tlb_miss;
  1007. crtc = intel_get_crtc_for_plane(dev, plane);
  1008. if (!intel_crtc_active(crtc)) {
  1009. *cursor_wm = cursor->guard_size;
  1010. *plane_wm = display->guard_size;
  1011. return false;
  1012. }
  1013. htotal = crtc->mode.htotal;
  1014. hdisplay = crtc->mode.hdisplay;
  1015. clock = crtc->mode.clock;
  1016. pixel_size = crtc->fb->bits_per_pixel / 8;
  1017. /* Use the small buffer method to calculate plane watermark */
  1018. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  1019. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  1020. if (tlb_miss > 0)
  1021. entries += tlb_miss;
  1022. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  1023. *plane_wm = entries + display->guard_size;
  1024. if (*plane_wm > (int)display->max_wm)
  1025. *plane_wm = display->max_wm;
  1026. /* Use the large buffer method to calculate cursor watermark */
  1027. line_time_us = ((htotal * 1000) / clock);
  1028. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  1029. entries = line_count * 64 * pixel_size;
  1030. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  1031. if (tlb_miss > 0)
  1032. entries += tlb_miss;
  1033. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1034. *cursor_wm = entries + cursor->guard_size;
  1035. if (*cursor_wm > (int)cursor->max_wm)
  1036. *cursor_wm = (int)cursor->max_wm;
  1037. return true;
  1038. }
  1039. /*
  1040. * Check the wm result.
  1041. *
  1042. * If any calculated watermark values is larger than the maximum value that
  1043. * can be programmed into the associated watermark register, that watermark
  1044. * must be disabled.
  1045. */
  1046. static bool g4x_check_srwm(struct drm_device *dev,
  1047. int display_wm, int cursor_wm,
  1048. const struct intel_watermark_params *display,
  1049. const struct intel_watermark_params *cursor)
  1050. {
  1051. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  1052. display_wm, cursor_wm);
  1053. if (display_wm > display->max_wm) {
  1054. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  1055. display_wm, display->max_wm);
  1056. return false;
  1057. }
  1058. if (cursor_wm > cursor->max_wm) {
  1059. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  1060. cursor_wm, cursor->max_wm);
  1061. return false;
  1062. }
  1063. if (!(display_wm || cursor_wm)) {
  1064. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  1065. return false;
  1066. }
  1067. return true;
  1068. }
  1069. static bool g4x_compute_srwm(struct drm_device *dev,
  1070. int plane,
  1071. int latency_ns,
  1072. const struct intel_watermark_params *display,
  1073. const struct intel_watermark_params *cursor,
  1074. int *display_wm, int *cursor_wm)
  1075. {
  1076. struct drm_crtc *crtc;
  1077. int hdisplay, htotal, pixel_size, clock;
  1078. unsigned long line_time_us;
  1079. int line_count, line_size;
  1080. int small, large;
  1081. int entries;
  1082. if (!latency_ns) {
  1083. *display_wm = *cursor_wm = 0;
  1084. return false;
  1085. }
  1086. crtc = intel_get_crtc_for_plane(dev, plane);
  1087. hdisplay = crtc->mode.hdisplay;
  1088. htotal = crtc->mode.htotal;
  1089. clock = crtc->mode.clock;
  1090. pixel_size = crtc->fb->bits_per_pixel / 8;
  1091. line_time_us = (htotal * 1000) / clock;
  1092. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1093. line_size = hdisplay * pixel_size;
  1094. /* Use the minimum of the small and large buffer method for primary */
  1095. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1096. large = line_count * line_size;
  1097. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1098. *display_wm = entries + display->guard_size;
  1099. /* calculate the self-refresh watermark for display cursor */
  1100. entries = line_count * pixel_size * 64;
  1101. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1102. *cursor_wm = entries + cursor->guard_size;
  1103. return g4x_check_srwm(dev,
  1104. *display_wm, *cursor_wm,
  1105. display, cursor);
  1106. }
  1107. static bool vlv_compute_drain_latency(struct drm_device *dev,
  1108. int plane,
  1109. int *plane_prec_mult,
  1110. int *plane_dl,
  1111. int *cursor_prec_mult,
  1112. int *cursor_dl)
  1113. {
  1114. struct drm_crtc *crtc;
  1115. int clock, pixel_size;
  1116. int entries;
  1117. crtc = intel_get_crtc_for_plane(dev, plane);
  1118. if (!intel_crtc_active(crtc))
  1119. return false;
  1120. clock = crtc->mode.clock; /* VESA DOT Clock */
  1121. pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
  1122. entries = (clock / 1000) * pixel_size;
  1123. *plane_prec_mult = (entries > 256) ?
  1124. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1125. *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
  1126. pixel_size);
  1127. entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
  1128. *cursor_prec_mult = (entries > 256) ?
  1129. DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
  1130. *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
  1131. return true;
  1132. }
  1133. /*
  1134. * Update drain latency registers of memory arbiter
  1135. *
  1136. * Valleyview SoC has a new memory arbiter and needs drain latency registers
  1137. * to be programmed. Each plane has a drain latency multiplier and a drain
  1138. * latency value.
  1139. */
  1140. static void vlv_update_drain_latency(struct drm_device *dev)
  1141. {
  1142. struct drm_i915_private *dev_priv = dev->dev_private;
  1143. int planea_prec, planea_dl, planeb_prec, planeb_dl;
  1144. int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
  1145. int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
  1146. either 16 or 32 */
  1147. /* For plane A, Cursor A */
  1148. if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
  1149. &cursor_prec_mult, &cursora_dl)) {
  1150. cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1151. DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
  1152. planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1153. DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
  1154. I915_WRITE(VLV_DDL1, cursora_prec |
  1155. (cursora_dl << DDL_CURSORA_SHIFT) |
  1156. planea_prec | planea_dl);
  1157. }
  1158. /* For plane B, Cursor B */
  1159. if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
  1160. &cursor_prec_mult, &cursorb_dl)) {
  1161. cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1162. DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
  1163. planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
  1164. DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
  1165. I915_WRITE(VLV_DDL2, cursorb_prec |
  1166. (cursorb_dl << DDL_CURSORB_SHIFT) |
  1167. planeb_prec | planeb_dl);
  1168. }
  1169. }
  1170. #define single_plane_enabled(mask) is_power_of_2(mask)
  1171. static void valleyview_update_wm(struct drm_device *dev)
  1172. {
  1173. static const int sr_latency_ns = 12000;
  1174. struct drm_i915_private *dev_priv = dev->dev_private;
  1175. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1176. int plane_sr, cursor_sr;
  1177. int ignore_plane_sr, ignore_cursor_sr;
  1178. unsigned int enabled = 0;
  1179. vlv_update_drain_latency(dev);
  1180. if (g4x_compute_wm0(dev, PIPE_A,
  1181. &valleyview_wm_info, latency_ns,
  1182. &valleyview_cursor_wm_info, latency_ns,
  1183. &planea_wm, &cursora_wm))
  1184. enabled |= 1 << PIPE_A;
  1185. if (g4x_compute_wm0(dev, PIPE_B,
  1186. &valleyview_wm_info, latency_ns,
  1187. &valleyview_cursor_wm_info, latency_ns,
  1188. &planeb_wm, &cursorb_wm))
  1189. enabled |= 1 << PIPE_B;
  1190. if (single_plane_enabled(enabled) &&
  1191. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1192. sr_latency_ns,
  1193. &valleyview_wm_info,
  1194. &valleyview_cursor_wm_info,
  1195. &plane_sr, &ignore_cursor_sr) &&
  1196. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1197. 2*sr_latency_ns,
  1198. &valleyview_wm_info,
  1199. &valleyview_cursor_wm_info,
  1200. &ignore_plane_sr, &cursor_sr)) {
  1201. I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
  1202. } else {
  1203. I915_WRITE(FW_BLC_SELF_VLV,
  1204. I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
  1205. plane_sr = cursor_sr = 0;
  1206. }
  1207. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1208. planea_wm, cursora_wm,
  1209. planeb_wm, cursorb_wm,
  1210. plane_sr, cursor_sr);
  1211. I915_WRITE(DSPFW1,
  1212. (plane_sr << DSPFW_SR_SHIFT) |
  1213. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1214. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1215. planea_wm);
  1216. I915_WRITE(DSPFW2,
  1217. (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
  1218. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1219. I915_WRITE(DSPFW3,
  1220. (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
  1221. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1222. }
  1223. static void g4x_update_wm(struct drm_device *dev)
  1224. {
  1225. static const int sr_latency_ns = 12000;
  1226. struct drm_i915_private *dev_priv = dev->dev_private;
  1227. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  1228. int plane_sr, cursor_sr;
  1229. unsigned int enabled = 0;
  1230. if (g4x_compute_wm0(dev, PIPE_A,
  1231. &g4x_wm_info, latency_ns,
  1232. &g4x_cursor_wm_info, latency_ns,
  1233. &planea_wm, &cursora_wm))
  1234. enabled |= 1 << PIPE_A;
  1235. if (g4x_compute_wm0(dev, PIPE_B,
  1236. &g4x_wm_info, latency_ns,
  1237. &g4x_cursor_wm_info, latency_ns,
  1238. &planeb_wm, &cursorb_wm))
  1239. enabled |= 1 << PIPE_B;
  1240. if (single_plane_enabled(enabled) &&
  1241. g4x_compute_srwm(dev, ffs(enabled) - 1,
  1242. sr_latency_ns,
  1243. &g4x_wm_info,
  1244. &g4x_cursor_wm_info,
  1245. &plane_sr, &cursor_sr)) {
  1246. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1247. } else {
  1248. I915_WRITE(FW_BLC_SELF,
  1249. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  1250. plane_sr = cursor_sr = 0;
  1251. }
  1252. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  1253. planea_wm, cursora_wm,
  1254. planeb_wm, cursorb_wm,
  1255. plane_sr, cursor_sr);
  1256. I915_WRITE(DSPFW1,
  1257. (plane_sr << DSPFW_SR_SHIFT) |
  1258. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  1259. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  1260. planea_wm);
  1261. I915_WRITE(DSPFW2,
  1262. (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
  1263. (cursora_wm << DSPFW_CURSORA_SHIFT));
  1264. /* HPLL off in SR has some issues on G4x... disable it */
  1265. I915_WRITE(DSPFW3,
  1266. (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
  1267. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1268. }
  1269. static void i965_update_wm(struct drm_device *dev)
  1270. {
  1271. struct drm_i915_private *dev_priv = dev->dev_private;
  1272. struct drm_crtc *crtc;
  1273. int srwm = 1;
  1274. int cursor_sr = 16;
  1275. /* Calc sr entries for one plane configs */
  1276. crtc = single_enabled_crtc(dev);
  1277. if (crtc) {
  1278. /* self-refresh has much higher latency */
  1279. static const int sr_latency_ns = 12000;
  1280. int clock = crtc->mode.clock;
  1281. int htotal = crtc->mode.htotal;
  1282. int hdisplay = crtc->mode.hdisplay;
  1283. int pixel_size = crtc->fb->bits_per_pixel / 8;
  1284. unsigned long line_time_us;
  1285. int entries;
  1286. line_time_us = ((htotal * 1000) / clock);
  1287. /* Use ns/us then divide to preserve precision */
  1288. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1289. pixel_size * hdisplay;
  1290. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  1291. srwm = I965_FIFO_SIZE - entries;
  1292. if (srwm < 0)
  1293. srwm = 1;
  1294. srwm &= 0x1ff;
  1295. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  1296. entries, srwm);
  1297. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1298. pixel_size * 64;
  1299. entries = DIV_ROUND_UP(entries,
  1300. i965_cursor_wm_info.cacheline_size);
  1301. cursor_sr = i965_cursor_wm_info.fifo_size -
  1302. (entries + i965_cursor_wm_info.guard_size);
  1303. if (cursor_sr > i965_cursor_wm_info.max_wm)
  1304. cursor_sr = i965_cursor_wm_info.max_wm;
  1305. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  1306. "cursor %d\n", srwm, cursor_sr);
  1307. if (IS_CRESTLINE(dev))
  1308. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  1309. } else {
  1310. /* Turn off self refresh if both pipes are enabled */
  1311. if (IS_CRESTLINE(dev))
  1312. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  1313. & ~FW_BLC_SELF_EN);
  1314. }
  1315. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  1316. srwm);
  1317. /* 965 has limitations... */
  1318. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  1319. (8 << 16) | (8 << 8) | (8 << 0));
  1320. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  1321. /* update cursor SR watermark */
  1322. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  1323. }
  1324. static void i9xx_update_wm(struct drm_device *dev)
  1325. {
  1326. struct drm_i915_private *dev_priv = dev->dev_private;
  1327. const struct intel_watermark_params *wm_info;
  1328. uint32_t fwater_lo;
  1329. uint32_t fwater_hi;
  1330. int cwm, srwm = 1;
  1331. int fifo_size;
  1332. int planea_wm, planeb_wm;
  1333. struct drm_crtc *crtc, *enabled = NULL;
  1334. if (IS_I945GM(dev))
  1335. wm_info = &i945_wm_info;
  1336. else if (!IS_GEN2(dev))
  1337. wm_info = &i915_wm_info;
  1338. else
  1339. wm_info = &i855_wm_info;
  1340. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  1341. crtc = intel_get_crtc_for_plane(dev, 0);
  1342. if (intel_crtc_active(crtc)) {
  1343. int cpp = crtc->fb->bits_per_pixel / 8;
  1344. if (IS_GEN2(dev))
  1345. cpp = 4;
  1346. planea_wm = intel_calculate_wm(crtc->mode.clock,
  1347. wm_info, fifo_size, cpp,
  1348. latency_ns);
  1349. enabled = crtc;
  1350. } else
  1351. planea_wm = fifo_size - wm_info->guard_size;
  1352. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  1353. crtc = intel_get_crtc_for_plane(dev, 1);
  1354. if (intel_crtc_active(crtc)) {
  1355. int cpp = crtc->fb->bits_per_pixel / 8;
  1356. if (IS_GEN2(dev))
  1357. cpp = 4;
  1358. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  1359. wm_info, fifo_size, cpp,
  1360. latency_ns);
  1361. if (enabled == NULL)
  1362. enabled = crtc;
  1363. else
  1364. enabled = NULL;
  1365. } else
  1366. planeb_wm = fifo_size - wm_info->guard_size;
  1367. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  1368. /*
  1369. * Overlay gets an aggressive default since video jitter is bad.
  1370. */
  1371. cwm = 2;
  1372. /* Play safe and disable self-refresh before adjusting watermarks. */
  1373. if (IS_I945G(dev) || IS_I945GM(dev))
  1374. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  1375. else if (IS_I915GM(dev))
  1376. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  1377. /* Calc sr entries for one plane configs */
  1378. if (HAS_FW_BLC(dev) && enabled) {
  1379. /* self-refresh has much higher latency */
  1380. static const int sr_latency_ns = 6000;
  1381. int clock = enabled->mode.clock;
  1382. int htotal = enabled->mode.htotal;
  1383. int hdisplay = enabled->mode.hdisplay;
  1384. int pixel_size = enabled->fb->bits_per_pixel / 8;
  1385. unsigned long line_time_us;
  1386. int entries;
  1387. line_time_us = (htotal * 1000) / clock;
  1388. /* Use ns/us then divide to preserve precision */
  1389. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  1390. pixel_size * hdisplay;
  1391. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  1392. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  1393. srwm = wm_info->fifo_size - entries;
  1394. if (srwm < 0)
  1395. srwm = 1;
  1396. if (IS_I945G(dev) || IS_I945GM(dev))
  1397. I915_WRITE(FW_BLC_SELF,
  1398. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  1399. else if (IS_I915GM(dev))
  1400. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  1401. }
  1402. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  1403. planea_wm, planeb_wm, cwm, srwm);
  1404. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  1405. fwater_hi = (cwm & 0x1f);
  1406. /* Set request length to 8 cachelines per fetch */
  1407. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  1408. fwater_hi = fwater_hi | (1 << 8);
  1409. I915_WRITE(FW_BLC, fwater_lo);
  1410. I915_WRITE(FW_BLC2, fwater_hi);
  1411. if (HAS_FW_BLC(dev)) {
  1412. if (enabled) {
  1413. if (IS_I945G(dev) || IS_I945GM(dev))
  1414. I915_WRITE(FW_BLC_SELF,
  1415. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  1416. else if (IS_I915GM(dev))
  1417. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  1418. DRM_DEBUG_KMS("memory self refresh enabled\n");
  1419. } else
  1420. DRM_DEBUG_KMS("memory self refresh disabled\n");
  1421. }
  1422. }
  1423. static void i830_update_wm(struct drm_device *dev)
  1424. {
  1425. struct drm_i915_private *dev_priv = dev->dev_private;
  1426. struct drm_crtc *crtc;
  1427. uint32_t fwater_lo;
  1428. int planea_wm;
  1429. crtc = single_enabled_crtc(dev);
  1430. if (crtc == NULL)
  1431. return;
  1432. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  1433. dev_priv->display.get_fifo_size(dev, 0),
  1434. 4, latency_ns);
  1435. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  1436. fwater_lo |= (3<<8) | planea_wm;
  1437. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  1438. I915_WRITE(FW_BLC, fwater_lo);
  1439. }
  1440. #define ILK_LP0_PLANE_LATENCY 700
  1441. #define ILK_LP0_CURSOR_LATENCY 1300
  1442. /*
  1443. * Check the wm result.
  1444. *
  1445. * If any calculated watermark values is larger than the maximum value that
  1446. * can be programmed into the associated watermark register, that watermark
  1447. * must be disabled.
  1448. */
  1449. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  1450. int fbc_wm, int display_wm, int cursor_wm,
  1451. const struct intel_watermark_params *display,
  1452. const struct intel_watermark_params *cursor)
  1453. {
  1454. struct drm_i915_private *dev_priv = dev->dev_private;
  1455. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  1456. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  1457. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  1458. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  1459. fbc_wm, SNB_FBC_MAX_SRWM, level);
  1460. /* fbc has it's own way to disable FBC WM */
  1461. I915_WRITE(DISP_ARB_CTL,
  1462. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  1463. return false;
  1464. } else if (INTEL_INFO(dev)->gen >= 6) {
  1465. /* enable FBC WM (except on ILK, where it must remain off) */
  1466. I915_WRITE(DISP_ARB_CTL,
  1467. I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
  1468. }
  1469. if (display_wm > display->max_wm) {
  1470. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  1471. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  1472. return false;
  1473. }
  1474. if (cursor_wm > cursor->max_wm) {
  1475. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  1476. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  1477. return false;
  1478. }
  1479. if (!(fbc_wm || display_wm || cursor_wm)) {
  1480. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  1481. return false;
  1482. }
  1483. return true;
  1484. }
  1485. /*
  1486. * Compute watermark values of WM[1-3],
  1487. */
  1488. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  1489. int latency_ns,
  1490. const struct intel_watermark_params *display,
  1491. const struct intel_watermark_params *cursor,
  1492. int *fbc_wm, int *display_wm, int *cursor_wm)
  1493. {
  1494. struct drm_crtc *crtc;
  1495. unsigned long line_time_us;
  1496. int hdisplay, htotal, pixel_size, clock;
  1497. int line_count, line_size;
  1498. int small, large;
  1499. int entries;
  1500. if (!latency_ns) {
  1501. *fbc_wm = *display_wm = *cursor_wm = 0;
  1502. return false;
  1503. }
  1504. crtc = intel_get_crtc_for_plane(dev, plane);
  1505. hdisplay = crtc->mode.hdisplay;
  1506. htotal = crtc->mode.htotal;
  1507. clock = crtc->mode.clock;
  1508. pixel_size = crtc->fb->bits_per_pixel / 8;
  1509. line_time_us = (htotal * 1000) / clock;
  1510. line_count = (latency_ns / line_time_us + 1000) / 1000;
  1511. line_size = hdisplay * pixel_size;
  1512. /* Use the minimum of the small and large buffer method for primary */
  1513. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  1514. large = line_count * line_size;
  1515. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  1516. *display_wm = entries + display->guard_size;
  1517. /*
  1518. * Spec says:
  1519. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  1520. */
  1521. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  1522. /* calculate the self-refresh watermark for display cursor */
  1523. entries = line_count * pixel_size * 64;
  1524. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  1525. *cursor_wm = entries + cursor->guard_size;
  1526. return ironlake_check_srwm(dev, level,
  1527. *fbc_wm, *display_wm, *cursor_wm,
  1528. display, cursor);
  1529. }
  1530. static void ironlake_update_wm(struct drm_device *dev)
  1531. {
  1532. struct drm_i915_private *dev_priv = dev->dev_private;
  1533. int fbc_wm, plane_wm, cursor_wm;
  1534. unsigned int enabled;
  1535. enabled = 0;
  1536. if (g4x_compute_wm0(dev, PIPE_A,
  1537. &ironlake_display_wm_info,
  1538. ILK_LP0_PLANE_LATENCY,
  1539. &ironlake_cursor_wm_info,
  1540. ILK_LP0_CURSOR_LATENCY,
  1541. &plane_wm, &cursor_wm)) {
  1542. I915_WRITE(WM0_PIPEA_ILK,
  1543. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1544. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1545. " plane %d, " "cursor: %d\n",
  1546. plane_wm, cursor_wm);
  1547. enabled |= 1 << PIPE_A;
  1548. }
  1549. if (g4x_compute_wm0(dev, PIPE_B,
  1550. &ironlake_display_wm_info,
  1551. ILK_LP0_PLANE_LATENCY,
  1552. &ironlake_cursor_wm_info,
  1553. ILK_LP0_CURSOR_LATENCY,
  1554. &plane_wm, &cursor_wm)) {
  1555. I915_WRITE(WM0_PIPEB_ILK,
  1556. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  1557. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1558. " plane %d, cursor: %d\n",
  1559. plane_wm, cursor_wm);
  1560. enabled |= 1 << PIPE_B;
  1561. }
  1562. /*
  1563. * Calculate and update the self-refresh watermark only when one
  1564. * display plane is used.
  1565. */
  1566. I915_WRITE(WM3_LP_ILK, 0);
  1567. I915_WRITE(WM2_LP_ILK, 0);
  1568. I915_WRITE(WM1_LP_ILK, 0);
  1569. if (!single_plane_enabled(enabled))
  1570. return;
  1571. enabled = ffs(enabled) - 1;
  1572. /* WM1 */
  1573. if (!ironlake_compute_srwm(dev, 1, enabled,
  1574. ILK_READ_WM1_LATENCY() * 500,
  1575. &ironlake_display_srwm_info,
  1576. &ironlake_cursor_srwm_info,
  1577. &fbc_wm, &plane_wm, &cursor_wm))
  1578. return;
  1579. I915_WRITE(WM1_LP_ILK,
  1580. WM1_LP_SR_EN |
  1581. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1582. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1583. (plane_wm << WM1_LP_SR_SHIFT) |
  1584. cursor_wm);
  1585. /* WM2 */
  1586. if (!ironlake_compute_srwm(dev, 2, enabled,
  1587. ILK_READ_WM2_LATENCY() * 500,
  1588. &ironlake_display_srwm_info,
  1589. &ironlake_cursor_srwm_info,
  1590. &fbc_wm, &plane_wm, &cursor_wm))
  1591. return;
  1592. I915_WRITE(WM2_LP_ILK,
  1593. WM2_LP_EN |
  1594. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1595. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1596. (plane_wm << WM1_LP_SR_SHIFT) |
  1597. cursor_wm);
  1598. /*
  1599. * WM3 is unsupported on ILK, probably because we don't have latency
  1600. * data for that power state
  1601. */
  1602. }
  1603. static void sandybridge_update_wm(struct drm_device *dev)
  1604. {
  1605. struct drm_i915_private *dev_priv = dev->dev_private;
  1606. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1607. u32 val;
  1608. int fbc_wm, plane_wm, cursor_wm;
  1609. unsigned int enabled;
  1610. enabled = 0;
  1611. if (g4x_compute_wm0(dev, PIPE_A,
  1612. &sandybridge_display_wm_info, latency,
  1613. &sandybridge_cursor_wm_info, latency,
  1614. &plane_wm, &cursor_wm)) {
  1615. val = I915_READ(WM0_PIPEA_ILK);
  1616. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1617. I915_WRITE(WM0_PIPEA_ILK, val |
  1618. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1619. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1620. " plane %d, " "cursor: %d\n",
  1621. plane_wm, cursor_wm);
  1622. enabled |= 1 << PIPE_A;
  1623. }
  1624. if (g4x_compute_wm0(dev, PIPE_B,
  1625. &sandybridge_display_wm_info, latency,
  1626. &sandybridge_cursor_wm_info, latency,
  1627. &plane_wm, &cursor_wm)) {
  1628. val = I915_READ(WM0_PIPEB_ILK);
  1629. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1630. I915_WRITE(WM0_PIPEB_ILK, val |
  1631. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1632. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1633. " plane %d, cursor: %d\n",
  1634. plane_wm, cursor_wm);
  1635. enabled |= 1 << PIPE_B;
  1636. }
  1637. /*
  1638. * Calculate and update the self-refresh watermark only when one
  1639. * display plane is used.
  1640. *
  1641. * SNB support 3 levels of watermark.
  1642. *
  1643. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1644. * and disabled in the descending order
  1645. *
  1646. */
  1647. I915_WRITE(WM3_LP_ILK, 0);
  1648. I915_WRITE(WM2_LP_ILK, 0);
  1649. I915_WRITE(WM1_LP_ILK, 0);
  1650. if (!single_plane_enabled(enabled) ||
  1651. dev_priv->sprite_scaling_enabled)
  1652. return;
  1653. enabled = ffs(enabled) - 1;
  1654. /* WM1 */
  1655. if (!ironlake_compute_srwm(dev, 1, enabled,
  1656. SNB_READ_WM1_LATENCY() * 500,
  1657. &sandybridge_display_srwm_info,
  1658. &sandybridge_cursor_srwm_info,
  1659. &fbc_wm, &plane_wm, &cursor_wm))
  1660. return;
  1661. I915_WRITE(WM1_LP_ILK,
  1662. WM1_LP_SR_EN |
  1663. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1664. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1665. (plane_wm << WM1_LP_SR_SHIFT) |
  1666. cursor_wm);
  1667. /* WM2 */
  1668. if (!ironlake_compute_srwm(dev, 2, enabled,
  1669. SNB_READ_WM2_LATENCY() * 500,
  1670. &sandybridge_display_srwm_info,
  1671. &sandybridge_cursor_srwm_info,
  1672. &fbc_wm, &plane_wm, &cursor_wm))
  1673. return;
  1674. I915_WRITE(WM2_LP_ILK,
  1675. WM2_LP_EN |
  1676. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1677. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1678. (plane_wm << WM1_LP_SR_SHIFT) |
  1679. cursor_wm);
  1680. /* WM3 */
  1681. if (!ironlake_compute_srwm(dev, 3, enabled,
  1682. SNB_READ_WM3_LATENCY() * 500,
  1683. &sandybridge_display_srwm_info,
  1684. &sandybridge_cursor_srwm_info,
  1685. &fbc_wm, &plane_wm, &cursor_wm))
  1686. return;
  1687. I915_WRITE(WM3_LP_ILK,
  1688. WM3_LP_EN |
  1689. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1690. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1691. (plane_wm << WM1_LP_SR_SHIFT) |
  1692. cursor_wm);
  1693. }
  1694. static void ivybridge_update_wm(struct drm_device *dev)
  1695. {
  1696. struct drm_i915_private *dev_priv = dev->dev_private;
  1697. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  1698. u32 val;
  1699. int fbc_wm, plane_wm, cursor_wm;
  1700. int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
  1701. unsigned int enabled;
  1702. enabled = 0;
  1703. if (g4x_compute_wm0(dev, PIPE_A,
  1704. &sandybridge_display_wm_info, latency,
  1705. &sandybridge_cursor_wm_info, latency,
  1706. &plane_wm, &cursor_wm)) {
  1707. val = I915_READ(WM0_PIPEA_ILK);
  1708. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1709. I915_WRITE(WM0_PIPEA_ILK, val |
  1710. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1711. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  1712. " plane %d, " "cursor: %d\n",
  1713. plane_wm, cursor_wm);
  1714. enabled |= 1 << PIPE_A;
  1715. }
  1716. if (g4x_compute_wm0(dev, PIPE_B,
  1717. &sandybridge_display_wm_info, latency,
  1718. &sandybridge_cursor_wm_info, latency,
  1719. &plane_wm, &cursor_wm)) {
  1720. val = I915_READ(WM0_PIPEB_ILK);
  1721. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1722. I915_WRITE(WM0_PIPEB_ILK, val |
  1723. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1724. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  1725. " plane %d, cursor: %d\n",
  1726. plane_wm, cursor_wm);
  1727. enabled |= 1 << PIPE_B;
  1728. }
  1729. if (g4x_compute_wm0(dev, PIPE_C,
  1730. &sandybridge_display_wm_info, latency,
  1731. &sandybridge_cursor_wm_info, latency,
  1732. &plane_wm, &cursor_wm)) {
  1733. val = I915_READ(WM0_PIPEC_IVB);
  1734. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  1735. I915_WRITE(WM0_PIPEC_IVB, val |
  1736. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  1737. DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  1738. " plane %d, cursor: %d\n",
  1739. plane_wm, cursor_wm);
  1740. enabled |= 1 << PIPE_C;
  1741. }
  1742. /*
  1743. * Calculate and update the self-refresh watermark only when one
  1744. * display plane is used.
  1745. *
  1746. * SNB support 3 levels of watermark.
  1747. *
  1748. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  1749. * and disabled in the descending order
  1750. *
  1751. */
  1752. I915_WRITE(WM3_LP_ILK, 0);
  1753. I915_WRITE(WM2_LP_ILK, 0);
  1754. I915_WRITE(WM1_LP_ILK, 0);
  1755. if (!single_plane_enabled(enabled) ||
  1756. dev_priv->sprite_scaling_enabled)
  1757. return;
  1758. enabled = ffs(enabled) - 1;
  1759. /* WM1 */
  1760. if (!ironlake_compute_srwm(dev, 1, enabled,
  1761. SNB_READ_WM1_LATENCY() * 500,
  1762. &sandybridge_display_srwm_info,
  1763. &sandybridge_cursor_srwm_info,
  1764. &fbc_wm, &plane_wm, &cursor_wm))
  1765. return;
  1766. I915_WRITE(WM1_LP_ILK,
  1767. WM1_LP_SR_EN |
  1768. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1769. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1770. (plane_wm << WM1_LP_SR_SHIFT) |
  1771. cursor_wm);
  1772. /* WM2 */
  1773. if (!ironlake_compute_srwm(dev, 2, enabled,
  1774. SNB_READ_WM2_LATENCY() * 500,
  1775. &sandybridge_display_srwm_info,
  1776. &sandybridge_cursor_srwm_info,
  1777. &fbc_wm, &plane_wm, &cursor_wm))
  1778. return;
  1779. I915_WRITE(WM2_LP_ILK,
  1780. WM2_LP_EN |
  1781. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1782. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1783. (plane_wm << WM1_LP_SR_SHIFT) |
  1784. cursor_wm);
  1785. /* WM3, note we have to correct the cursor latency */
  1786. if (!ironlake_compute_srwm(dev, 3, enabled,
  1787. SNB_READ_WM3_LATENCY() * 500,
  1788. &sandybridge_display_srwm_info,
  1789. &sandybridge_cursor_srwm_info,
  1790. &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
  1791. !ironlake_compute_srwm(dev, 3, enabled,
  1792. 2 * SNB_READ_WM3_LATENCY() * 500,
  1793. &sandybridge_display_srwm_info,
  1794. &sandybridge_cursor_srwm_info,
  1795. &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
  1796. return;
  1797. I915_WRITE(WM3_LP_ILK,
  1798. WM3_LP_EN |
  1799. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  1800. (fbc_wm << WM1_LP_FBC_SHIFT) |
  1801. (plane_wm << WM1_LP_SR_SHIFT) |
  1802. cursor_wm);
  1803. }
  1804. static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
  1805. struct drm_crtc *crtc)
  1806. {
  1807. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1808. uint32_t pixel_rate, pfit_size;
  1809. pixel_rate = intel_crtc->config.adjusted_mode.clock;
  1810. /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
  1811. * adjust the pixel_rate here. */
  1812. pfit_size = intel_crtc->config.pch_pfit.size;
  1813. if (pfit_size) {
  1814. uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
  1815. pipe_w = intel_crtc->config.requested_mode.hdisplay;
  1816. pipe_h = intel_crtc->config.requested_mode.vdisplay;
  1817. pfit_w = (pfit_size >> 16) & 0xFFFF;
  1818. pfit_h = pfit_size & 0xFFFF;
  1819. if (pipe_w < pfit_w)
  1820. pipe_w = pfit_w;
  1821. if (pipe_h < pfit_h)
  1822. pipe_h = pfit_h;
  1823. pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
  1824. pfit_w * pfit_h);
  1825. }
  1826. return pixel_rate;
  1827. }
  1828. static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
  1829. uint32_t latency)
  1830. {
  1831. uint64_t ret;
  1832. ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
  1833. ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
  1834. return ret;
  1835. }
  1836. static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
  1837. uint32_t horiz_pixels, uint8_t bytes_per_pixel,
  1838. uint32_t latency)
  1839. {
  1840. uint32_t ret;
  1841. ret = (latency * pixel_rate) / (pipe_htotal * 10000);
  1842. ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
  1843. ret = DIV_ROUND_UP(ret, 64) + 2;
  1844. return ret;
  1845. }
  1846. static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
  1847. uint8_t bytes_per_pixel)
  1848. {
  1849. return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
  1850. }
  1851. struct hsw_pipe_wm_parameters {
  1852. bool active;
  1853. bool sprite_enabled;
  1854. uint8_t pri_bytes_per_pixel;
  1855. uint8_t spr_bytes_per_pixel;
  1856. uint8_t cur_bytes_per_pixel;
  1857. uint32_t pri_horiz_pixels;
  1858. uint32_t spr_horiz_pixels;
  1859. uint32_t cur_horiz_pixels;
  1860. uint32_t pipe_htotal;
  1861. uint32_t pixel_rate;
  1862. };
  1863. struct hsw_wm_maximums {
  1864. uint16_t pri;
  1865. uint16_t spr;
  1866. uint16_t cur;
  1867. uint16_t fbc;
  1868. };
  1869. struct hsw_lp_wm_result {
  1870. bool enable;
  1871. bool fbc_enable;
  1872. uint32_t pri_val;
  1873. uint32_t spr_val;
  1874. uint32_t cur_val;
  1875. uint32_t fbc_val;
  1876. };
  1877. struct hsw_wm_values {
  1878. uint32_t wm_pipe[3];
  1879. uint32_t wm_lp[3];
  1880. uint32_t wm_lp_spr[3];
  1881. uint32_t wm_linetime[3];
  1882. bool enable_fbc_wm;
  1883. };
  1884. enum hsw_data_buf_partitioning {
  1885. HSW_DATA_BUF_PART_1_2,
  1886. HSW_DATA_BUF_PART_5_6,
  1887. };
  1888. /* For both WM_PIPE and WM_LP. */
  1889. static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
  1890. uint32_t mem_value,
  1891. bool is_lp)
  1892. {
  1893. uint32_t method1, method2;
  1894. /* TODO: for now, assume the primary plane is always enabled. */
  1895. if (!params->active)
  1896. return 0;
  1897. method1 = hsw_wm_method1(params->pixel_rate,
  1898. params->pri_bytes_per_pixel,
  1899. mem_value);
  1900. if (!is_lp)
  1901. return method1;
  1902. method2 = hsw_wm_method2(params->pixel_rate,
  1903. params->pipe_htotal,
  1904. params->pri_horiz_pixels,
  1905. params->pri_bytes_per_pixel,
  1906. mem_value);
  1907. return min(method1, method2);
  1908. }
  1909. /* For both WM_PIPE and WM_LP. */
  1910. static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
  1911. uint32_t mem_value)
  1912. {
  1913. uint32_t method1, method2;
  1914. if (!params->active || !params->sprite_enabled)
  1915. return 0;
  1916. method1 = hsw_wm_method1(params->pixel_rate,
  1917. params->spr_bytes_per_pixel,
  1918. mem_value);
  1919. method2 = hsw_wm_method2(params->pixel_rate,
  1920. params->pipe_htotal,
  1921. params->spr_horiz_pixels,
  1922. params->spr_bytes_per_pixel,
  1923. mem_value);
  1924. return min(method1, method2);
  1925. }
  1926. /* For both WM_PIPE and WM_LP. */
  1927. static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
  1928. uint32_t mem_value)
  1929. {
  1930. if (!params->active)
  1931. return 0;
  1932. return hsw_wm_method2(params->pixel_rate,
  1933. params->pipe_htotal,
  1934. params->cur_horiz_pixels,
  1935. params->cur_bytes_per_pixel,
  1936. mem_value);
  1937. }
  1938. /* Only for WM_LP. */
  1939. static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
  1940. uint32_t pri_val,
  1941. uint32_t mem_value)
  1942. {
  1943. if (!params->active)
  1944. return 0;
  1945. return hsw_wm_fbc(pri_val,
  1946. params->pri_horiz_pixels,
  1947. params->pri_bytes_per_pixel);
  1948. }
  1949. static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
  1950. struct hsw_pipe_wm_parameters *params,
  1951. struct hsw_lp_wm_result *result)
  1952. {
  1953. enum pipe pipe;
  1954. uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
  1955. for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
  1956. struct hsw_pipe_wm_parameters *p = &params[pipe];
  1957. pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
  1958. spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
  1959. cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
  1960. fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
  1961. }
  1962. result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
  1963. result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
  1964. result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
  1965. result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
  1966. if (result->fbc_val > max->fbc) {
  1967. result->fbc_enable = false;
  1968. result->fbc_val = 0;
  1969. } else {
  1970. result->fbc_enable = true;
  1971. }
  1972. result->enable = result->pri_val <= max->pri &&
  1973. result->spr_val <= max->spr &&
  1974. result->cur_val <= max->cur;
  1975. return result->enable;
  1976. }
  1977. static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
  1978. uint32_t mem_value, enum pipe pipe,
  1979. struct hsw_pipe_wm_parameters *params)
  1980. {
  1981. uint32_t pri_val, cur_val, spr_val;
  1982. pri_val = hsw_compute_pri_wm(params, mem_value, false);
  1983. spr_val = hsw_compute_spr_wm(params, mem_value);
  1984. cur_val = hsw_compute_cur_wm(params, mem_value);
  1985. WARN(pri_val > 127,
  1986. "Primary WM error, mode not supported for pipe %c\n",
  1987. pipe_name(pipe));
  1988. WARN(spr_val > 127,
  1989. "Sprite WM error, mode not supported for pipe %c\n",
  1990. pipe_name(pipe));
  1991. WARN(cur_val > 63,
  1992. "Cursor WM error, mode not supported for pipe %c\n",
  1993. pipe_name(pipe));
  1994. return (pri_val << WM0_PIPE_PLANE_SHIFT) |
  1995. (spr_val << WM0_PIPE_SPRITE_SHIFT) |
  1996. cur_val;
  1997. }
  1998. static uint32_t
  1999. hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
  2000. {
  2001. struct drm_i915_private *dev_priv = dev->dev_private;
  2002. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2003. struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
  2004. u32 linetime, ips_linetime;
  2005. if (!intel_crtc_active(crtc))
  2006. return 0;
  2007. /* The WM are computed with base on how long it takes to fill a single
  2008. * row at the given clock rate, multiplied by 8.
  2009. * */
  2010. linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
  2011. ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
  2012. intel_ddi_get_cdclk_freq(dev_priv));
  2013. return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
  2014. PIPE_WM_LINETIME_TIME(linetime);
  2015. }
  2016. static void hsw_compute_wm_parameters(struct drm_device *dev,
  2017. struct hsw_pipe_wm_parameters *params,
  2018. uint32_t *wm,
  2019. struct hsw_wm_maximums *lp_max_1_2,
  2020. struct hsw_wm_maximums *lp_max_5_6)
  2021. {
  2022. struct drm_i915_private *dev_priv = dev->dev_private;
  2023. struct drm_crtc *crtc;
  2024. struct drm_plane *plane;
  2025. uint64_t sskpd = I915_READ64(MCH_SSKPD);
  2026. enum pipe pipe;
  2027. int pipes_active = 0, sprites_enabled = 0;
  2028. if ((sskpd >> 56) & 0xFF)
  2029. wm[0] = (sskpd >> 56) & 0xFF;
  2030. else
  2031. wm[0] = sskpd & 0xF;
  2032. wm[1] = ((sskpd >> 4) & 0xFF) * 5;
  2033. wm[2] = ((sskpd >> 12) & 0xFF) * 5;
  2034. wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
  2035. wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
  2036. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2037. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2038. struct hsw_pipe_wm_parameters *p;
  2039. pipe = intel_crtc->pipe;
  2040. p = &params[pipe];
  2041. p->active = intel_crtc_active(crtc);
  2042. if (!p->active)
  2043. continue;
  2044. pipes_active++;
  2045. p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
  2046. p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
  2047. p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
  2048. p->cur_bytes_per_pixel = 4;
  2049. p->pri_horiz_pixels =
  2050. intel_crtc->config.requested_mode.hdisplay;
  2051. p->cur_horiz_pixels = 64;
  2052. }
  2053. list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  2054. struct intel_plane *intel_plane = to_intel_plane(plane);
  2055. struct hsw_pipe_wm_parameters *p;
  2056. pipe = intel_plane->pipe;
  2057. p = &params[pipe];
  2058. p->sprite_enabled = intel_plane->wm.enable;
  2059. p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
  2060. p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
  2061. if (p->sprite_enabled)
  2062. sprites_enabled++;
  2063. }
  2064. if (pipes_active > 1) {
  2065. lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
  2066. lp_max_1_2->spr = lp_max_5_6->spr = 128;
  2067. lp_max_1_2->cur = lp_max_5_6->cur = 64;
  2068. } else {
  2069. lp_max_1_2->pri = sprites_enabled ? 384 : 768;
  2070. lp_max_5_6->pri = sprites_enabled ? 128 : 768;
  2071. lp_max_1_2->spr = 384;
  2072. lp_max_5_6->spr = 640;
  2073. lp_max_1_2->cur = lp_max_5_6->cur = 255;
  2074. }
  2075. lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
  2076. }
  2077. static void hsw_compute_wm_results(struct drm_device *dev,
  2078. struct hsw_pipe_wm_parameters *params,
  2079. uint32_t *wm,
  2080. struct hsw_wm_maximums *lp_maximums,
  2081. struct hsw_wm_values *results)
  2082. {
  2083. struct drm_i915_private *dev_priv = dev->dev_private;
  2084. struct drm_crtc *crtc;
  2085. struct hsw_lp_wm_result lp_results[4] = {};
  2086. enum pipe pipe;
  2087. int level, max_level, wm_lp;
  2088. for (level = 1; level <= 4; level++)
  2089. if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
  2090. &lp_results[level - 1]))
  2091. break;
  2092. max_level = level - 1;
  2093. /* The spec says it is preferred to disable FBC WMs instead of disabling
  2094. * a WM level. */
  2095. results->enable_fbc_wm = true;
  2096. for (level = 1; level <= max_level; level++) {
  2097. if (!lp_results[level - 1].fbc_enable) {
  2098. results->enable_fbc_wm = false;
  2099. break;
  2100. }
  2101. }
  2102. memset(results, 0, sizeof(*results));
  2103. for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
  2104. const struct hsw_lp_wm_result *r;
  2105. level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
  2106. if (level > max_level)
  2107. break;
  2108. r = &lp_results[level - 1];
  2109. results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
  2110. r->fbc_val,
  2111. r->pri_val,
  2112. r->cur_val);
  2113. results->wm_lp_spr[wm_lp - 1] = r->spr_val;
  2114. }
  2115. for_each_pipe(pipe)
  2116. results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
  2117. pipe,
  2118. &params[pipe]);
  2119. for_each_pipe(pipe) {
  2120. crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  2121. results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
  2122. }
  2123. }
  2124. /* Find the result with the highest level enabled. Check for enable_fbc_wm in
  2125. * case both are at the same level. Prefer r1 in case they're the same. */
  2126. struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
  2127. struct hsw_wm_values *r2)
  2128. {
  2129. int i, val_r1 = 0, val_r2 = 0;
  2130. for (i = 0; i < 3; i++) {
  2131. if (r1->wm_lp[i] & WM3_LP_EN)
  2132. val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
  2133. if (r2->wm_lp[i] & WM3_LP_EN)
  2134. val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
  2135. }
  2136. if (val_r1 == val_r2) {
  2137. if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
  2138. return r2;
  2139. else
  2140. return r1;
  2141. } else if (val_r1 > val_r2) {
  2142. return r1;
  2143. } else {
  2144. return r2;
  2145. }
  2146. }
  2147. /*
  2148. * The spec says we shouldn't write when we don't need, because every write
  2149. * causes WMs to be re-evaluated, expending some power.
  2150. */
  2151. static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
  2152. struct hsw_wm_values *results,
  2153. enum hsw_data_buf_partitioning partitioning)
  2154. {
  2155. struct hsw_wm_values previous;
  2156. uint32_t val;
  2157. enum hsw_data_buf_partitioning prev_partitioning;
  2158. bool prev_enable_fbc_wm;
  2159. previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
  2160. previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
  2161. previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
  2162. previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
  2163. previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
  2164. previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
  2165. previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
  2166. previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
  2167. previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
  2168. previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
  2169. previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
  2170. previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
  2171. prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
  2172. HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
  2173. prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
  2174. if (memcmp(results->wm_pipe, previous.wm_pipe,
  2175. sizeof(results->wm_pipe)) == 0 &&
  2176. memcmp(results->wm_lp, previous.wm_lp,
  2177. sizeof(results->wm_lp)) == 0 &&
  2178. memcmp(results->wm_lp_spr, previous.wm_lp_spr,
  2179. sizeof(results->wm_lp_spr)) == 0 &&
  2180. memcmp(results->wm_linetime, previous.wm_linetime,
  2181. sizeof(results->wm_linetime)) == 0 &&
  2182. partitioning == prev_partitioning &&
  2183. results->enable_fbc_wm == prev_enable_fbc_wm)
  2184. return;
  2185. if (previous.wm_lp[2] != 0)
  2186. I915_WRITE(WM3_LP_ILK, 0);
  2187. if (previous.wm_lp[1] != 0)
  2188. I915_WRITE(WM2_LP_ILK, 0);
  2189. if (previous.wm_lp[0] != 0)
  2190. I915_WRITE(WM1_LP_ILK, 0);
  2191. if (previous.wm_pipe[0] != results->wm_pipe[0])
  2192. I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
  2193. if (previous.wm_pipe[1] != results->wm_pipe[1])
  2194. I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
  2195. if (previous.wm_pipe[2] != results->wm_pipe[2])
  2196. I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
  2197. if (previous.wm_linetime[0] != results->wm_linetime[0])
  2198. I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
  2199. if (previous.wm_linetime[1] != results->wm_linetime[1])
  2200. I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
  2201. if (previous.wm_linetime[2] != results->wm_linetime[2])
  2202. I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
  2203. if (prev_partitioning != partitioning) {
  2204. val = I915_READ(WM_MISC);
  2205. if (partitioning == HSW_DATA_BUF_PART_1_2)
  2206. val &= ~WM_MISC_DATA_PARTITION_5_6;
  2207. else
  2208. val |= WM_MISC_DATA_PARTITION_5_6;
  2209. I915_WRITE(WM_MISC, val);
  2210. }
  2211. if (prev_enable_fbc_wm != results->enable_fbc_wm) {
  2212. val = I915_READ(DISP_ARB_CTL);
  2213. if (results->enable_fbc_wm)
  2214. val &= ~DISP_FBC_WM_DIS;
  2215. else
  2216. val |= DISP_FBC_WM_DIS;
  2217. I915_WRITE(DISP_ARB_CTL, val);
  2218. }
  2219. if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
  2220. I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
  2221. if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
  2222. I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
  2223. if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
  2224. I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
  2225. if (results->wm_lp[0] != 0)
  2226. I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
  2227. if (results->wm_lp[1] != 0)
  2228. I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
  2229. if (results->wm_lp[2] != 0)
  2230. I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
  2231. }
  2232. static void haswell_update_wm(struct drm_device *dev)
  2233. {
  2234. struct drm_i915_private *dev_priv = dev->dev_private;
  2235. struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
  2236. struct hsw_pipe_wm_parameters params[3];
  2237. struct hsw_wm_values results_1_2, results_5_6, *best_results;
  2238. uint32_t wm[5];
  2239. enum hsw_data_buf_partitioning partitioning;
  2240. hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
  2241. hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
  2242. if (lp_max_1_2.pri != lp_max_5_6.pri) {
  2243. hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
  2244. &results_5_6);
  2245. best_results = hsw_find_best_result(&results_1_2, &results_5_6);
  2246. } else {
  2247. best_results = &results_1_2;
  2248. }
  2249. partitioning = (best_results == &results_1_2) ?
  2250. HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
  2251. hsw_write_wm_values(dev_priv, best_results, partitioning);
  2252. }
  2253. static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
  2254. uint32_t sprite_width, int pixel_size,
  2255. bool enable)
  2256. {
  2257. struct drm_plane *plane;
  2258. list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  2259. struct intel_plane *intel_plane = to_intel_plane(plane);
  2260. if (intel_plane->pipe == pipe) {
  2261. intel_plane->wm.enable = enable;
  2262. intel_plane->wm.horiz_pixels = sprite_width + 1;
  2263. intel_plane->wm.bytes_per_pixel = pixel_size;
  2264. break;
  2265. }
  2266. }
  2267. haswell_update_wm(dev);
  2268. }
  2269. static bool
  2270. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  2271. uint32_t sprite_width, int pixel_size,
  2272. const struct intel_watermark_params *display,
  2273. int display_latency_ns, int *sprite_wm)
  2274. {
  2275. struct drm_crtc *crtc;
  2276. int clock;
  2277. int entries, tlb_miss;
  2278. crtc = intel_get_crtc_for_plane(dev, plane);
  2279. if (!intel_crtc_active(crtc)) {
  2280. *sprite_wm = display->guard_size;
  2281. return false;
  2282. }
  2283. clock = crtc->mode.clock;
  2284. /* Use the small buffer method to calculate the sprite watermark */
  2285. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  2286. tlb_miss = display->fifo_size*display->cacheline_size -
  2287. sprite_width * 8;
  2288. if (tlb_miss > 0)
  2289. entries += tlb_miss;
  2290. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  2291. *sprite_wm = entries + display->guard_size;
  2292. if (*sprite_wm > (int)display->max_wm)
  2293. *sprite_wm = display->max_wm;
  2294. return true;
  2295. }
  2296. static bool
  2297. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  2298. uint32_t sprite_width, int pixel_size,
  2299. const struct intel_watermark_params *display,
  2300. int latency_ns, int *sprite_wm)
  2301. {
  2302. struct drm_crtc *crtc;
  2303. unsigned long line_time_us;
  2304. int clock;
  2305. int line_count, line_size;
  2306. int small, large;
  2307. int entries;
  2308. if (!latency_ns) {
  2309. *sprite_wm = 0;
  2310. return false;
  2311. }
  2312. crtc = intel_get_crtc_for_plane(dev, plane);
  2313. clock = crtc->mode.clock;
  2314. if (!clock) {
  2315. *sprite_wm = 0;
  2316. return false;
  2317. }
  2318. line_time_us = (sprite_width * 1000) / clock;
  2319. if (!line_time_us) {
  2320. *sprite_wm = 0;
  2321. return false;
  2322. }
  2323. line_count = (latency_ns / line_time_us + 1000) / 1000;
  2324. line_size = sprite_width * pixel_size;
  2325. /* Use the minimum of the small and large buffer method for primary */
  2326. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  2327. large = line_count * line_size;
  2328. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  2329. *sprite_wm = entries + display->guard_size;
  2330. return *sprite_wm > 0x3ff ? false : true;
  2331. }
  2332. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  2333. uint32_t sprite_width, int pixel_size,
  2334. bool enable)
  2335. {
  2336. struct drm_i915_private *dev_priv = dev->dev_private;
  2337. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  2338. u32 val;
  2339. int sprite_wm, reg;
  2340. int ret;
  2341. if (!enable)
  2342. return;
  2343. switch (pipe) {
  2344. case 0:
  2345. reg = WM0_PIPEA_ILK;
  2346. break;
  2347. case 1:
  2348. reg = WM0_PIPEB_ILK;
  2349. break;
  2350. case 2:
  2351. reg = WM0_PIPEC_IVB;
  2352. break;
  2353. default:
  2354. return; /* bad pipe */
  2355. }
  2356. ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  2357. &sandybridge_display_wm_info,
  2358. latency, &sprite_wm);
  2359. if (!ret) {
  2360. DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
  2361. pipe_name(pipe));
  2362. return;
  2363. }
  2364. val = I915_READ(reg);
  2365. val &= ~WM0_PIPE_SPRITE_MASK;
  2366. I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  2367. DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
  2368. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2369. pixel_size,
  2370. &sandybridge_display_srwm_info,
  2371. SNB_READ_WM1_LATENCY() * 500,
  2372. &sprite_wm);
  2373. if (!ret) {
  2374. DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
  2375. pipe_name(pipe));
  2376. return;
  2377. }
  2378. I915_WRITE(WM1S_LP_ILK, sprite_wm);
  2379. /* Only IVB has two more LP watermarks for sprite */
  2380. if (!IS_IVYBRIDGE(dev))
  2381. return;
  2382. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2383. pixel_size,
  2384. &sandybridge_display_srwm_info,
  2385. SNB_READ_WM2_LATENCY() * 500,
  2386. &sprite_wm);
  2387. if (!ret) {
  2388. DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
  2389. pipe_name(pipe));
  2390. return;
  2391. }
  2392. I915_WRITE(WM2S_LP_IVB, sprite_wm);
  2393. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  2394. pixel_size,
  2395. &sandybridge_display_srwm_info,
  2396. SNB_READ_WM3_LATENCY() * 500,
  2397. &sprite_wm);
  2398. if (!ret) {
  2399. DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
  2400. pipe_name(pipe));
  2401. return;
  2402. }
  2403. I915_WRITE(WM3S_LP_IVB, sprite_wm);
  2404. }
  2405. /**
  2406. * intel_update_watermarks - update FIFO watermark values based on current modes
  2407. *
  2408. * Calculate watermark values for the various WM regs based on current mode
  2409. * and plane configuration.
  2410. *
  2411. * There are several cases to deal with here:
  2412. * - normal (i.e. non-self-refresh)
  2413. * - self-refresh (SR) mode
  2414. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2415. * - lines are small relative to FIFO size (buffer can hold more than 2
  2416. * lines), so need to account for TLB latency
  2417. *
  2418. * The normal calculation is:
  2419. * watermark = dotclock * bytes per pixel * latency
  2420. * where latency is platform & configuration dependent (we assume pessimal
  2421. * values here).
  2422. *
  2423. * The SR calculation is:
  2424. * watermark = (trunc(latency/line time)+1) * surface width *
  2425. * bytes per pixel
  2426. * where
  2427. * line time = htotal / dotclock
  2428. * surface width = hdisplay for normal plane and 64 for cursor
  2429. * and latency is assumed to be high, as above.
  2430. *
  2431. * The final value programmed to the register should always be rounded up,
  2432. * and include an extra 2 entries to account for clock crossings.
  2433. *
  2434. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2435. * to set the non-SR watermarks to 8.
  2436. */
  2437. void intel_update_watermarks(struct drm_device *dev)
  2438. {
  2439. struct drm_i915_private *dev_priv = dev->dev_private;
  2440. if (dev_priv->display.update_wm)
  2441. dev_priv->display.update_wm(dev);
  2442. }
  2443. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  2444. uint32_t sprite_width, int pixel_size,
  2445. bool enable)
  2446. {
  2447. struct drm_i915_private *dev_priv = dev->dev_private;
  2448. if (dev_priv->display.update_sprite_wm)
  2449. dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  2450. pixel_size, enable);
  2451. }
  2452. static struct drm_i915_gem_object *
  2453. intel_alloc_context_page(struct drm_device *dev)
  2454. {
  2455. struct drm_i915_gem_object *ctx;
  2456. int ret;
  2457. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2458. ctx = i915_gem_alloc_object(dev, 4096);
  2459. if (!ctx) {
  2460. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  2461. return NULL;
  2462. }
  2463. ret = i915_gem_object_pin(ctx, 4096, true, false);
  2464. if (ret) {
  2465. DRM_ERROR("failed to pin power context: %d\n", ret);
  2466. goto err_unref;
  2467. }
  2468. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  2469. if (ret) {
  2470. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  2471. goto err_unpin;
  2472. }
  2473. return ctx;
  2474. err_unpin:
  2475. i915_gem_object_unpin(ctx);
  2476. err_unref:
  2477. drm_gem_object_unreference(&ctx->base);
  2478. return NULL;
  2479. }
  2480. /**
  2481. * Lock protecting IPS related data structures
  2482. */
  2483. DEFINE_SPINLOCK(mchdev_lock);
  2484. /* Global for IPS driver to get at the current i915 device. Protected by
  2485. * mchdev_lock. */
  2486. static struct drm_i915_private *i915_mch_dev;
  2487. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  2488. {
  2489. struct drm_i915_private *dev_priv = dev->dev_private;
  2490. u16 rgvswctl;
  2491. assert_spin_locked(&mchdev_lock);
  2492. rgvswctl = I915_READ16(MEMSWCTL);
  2493. if (rgvswctl & MEMCTL_CMD_STS) {
  2494. DRM_DEBUG("gpu busy, RCS change rejected\n");
  2495. return false; /* still busy with another command */
  2496. }
  2497. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  2498. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  2499. I915_WRITE16(MEMSWCTL, rgvswctl);
  2500. POSTING_READ16(MEMSWCTL);
  2501. rgvswctl |= MEMCTL_CMD_STS;
  2502. I915_WRITE16(MEMSWCTL, rgvswctl);
  2503. return true;
  2504. }
  2505. static void ironlake_enable_drps(struct drm_device *dev)
  2506. {
  2507. struct drm_i915_private *dev_priv = dev->dev_private;
  2508. u32 rgvmodectl = I915_READ(MEMMODECTL);
  2509. u8 fmax, fmin, fstart, vstart;
  2510. spin_lock_irq(&mchdev_lock);
  2511. /* Enable temp reporting */
  2512. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  2513. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  2514. /* 100ms RC evaluation intervals */
  2515. I915_WRITE(RCUPEI, 100000);
  2516. I915_WRITE(RCDNEI, 100000);
  2517. /* Set max/min thresholds to 90ms and 80ms respectively */
  2518. I915_WRITE(RCBMAXAVG, 90000);
  2519. I915_WRITE(RCBMINAVG, 80000);
  2520. I915_WRITE(MEMIHYST, 1);
  2521. /* Set up min, max, and cur for interrupt handling */
  2522. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  2523. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  2524. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  2525. MEMMODE_FSTART_SHIFT;
  2526. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  2527. PXVFREQ_PX_SHIFT;
  2528. dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
  2529. dev_priv->ips.fstart = fstart;
  2530. dev_priv->ips.max_delay = fstart;
  2531. dev_priv->ips.min_delay = fmin;
  2532. dev_priv->ips.cur_delay = fstart;
  2533. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  2534. fmax, fmin, fstart);
  2535. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  2536. /*
  2537. * Interrupts will be enabled in ironlake_irq_postinstall
  2538. */
  2539. I915_WRITE(VIDSTART, vstart);
  2540. POSTING_READ(VIDSTART);
  2541. rgvmodectl |= MEMMODE_SWMODE_EN;
  2542. I915_WRITE(MEMMODECTL, rgvmodectl);
  2543. if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  2544. DRM_ERROR("stuck trying to change perf mode\n");
  2545. mdelay(1);
  2546. ironlake_set_drps(dev, fstart);
  2547. dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  2548. I915_READ(0x112e0);
  2549. dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
  2550. dev_priv->ips.last_count2 = I915_READ(0x112f4);
  2551. getrawmonotonic(&dev_priv->ips.last_time2);
  2552. spin_unlock_irq(&mchdev_lock);
  2553. }
  2554. static void ironlake_disable_drps(struct drm_device *dev)
  2555. {
  2556. struct drm_i915_private *dev_priv = dev->dev_private;
  2557. u16 rgvswctl;
  2558. spin_lock_irq(&mchdev_lock);
  2559. rgvswctl = I915_READ16(MEMSWCTL);
  2560. /* Ack interrupts, disable EFC interrupt */
  2561. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  2562. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  2563. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  2564. I915_WRITE(DEIIR, DE_PCU_EVENT);
  2565. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  2566. /* Go back to the starting frequency */
  2567. ironlake_set_drps(dev, dev_priv->ips.fstart);
  2568. mdelay(1);
  2569. rgvswctl |= MEMCTL_CMD_STS;
  2570. I915_WRITE(MEMSWCTL, rgvswctl);
  2571. mdelay(1);
  2572. spin_unlock_irq(&mchdev_lock);
  2573. }
  2574. /* There's a funny hw issue where the hw returns all 0 when reading from
  2575. * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
  2576. * ourselves, instead of doing a rmw cycle (which might result in us clearing
  2577. * all limits and the gpu stuck at whatever frequency it is at atm).
  2578. */
  2579. static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
  2580. {
  2581. u32 limits;
  2582. limits = 0;
  2583. if (*val >= dev_priv->rps.max_delay)
  2584. *val = dev_priv->rps.max_delay;
  2585. limits |= dev_priv->rps.max_delay << 24;
  2586. /* Only set the down limit when we've reached the lowest level to avoid
  2587. * getting more interrupts, otherwise leave this clear. This prevents a
  2588. * race in the hw when coming out of rc6: There's a tiny window where
  2589. * the hw runs at the minimal clock before selecting the desired
  2590. * frequency, if the down threshold expires in that window we will not
  2591. * receive a down interrupt. */
  2592. if (*val <= dev_priv->rps.min_delay) {
  2593. *val = dev_priv->rps.min_delay;
  2594. limits |= dev_priv->rps.min_delay << 16;
  2595. }
  2596. return limits;
  2597. }
  2598. void gen6_set_rps(struct drm_device *dev, u8 val)
  2599. {
  2600. struct drm_i915_private *dev_priv = dev->dev_private;
  2601. u32 limits = gen6_rps_limits(dev_priv, &val);
  2602. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2603. WARN_ON(val > dev_priv->rps.max_delay);
  2604. WARN_ON(val < dev_priv->rps.min_delay);
  2605. if (val == dev_priv->rps.cur_delay)
  2606. return;
  2607. if (IS_HASWELL(dev))
  2608. I915_WRITE(GEN6_RPNSWREQ,
  2609. HSW_FREQUENCY(val));
  2610. else
  2611. I915_WRITE(GEN6_RPNSWREQ,
  2612. GEN6_FREQUENCY(val) |
  2613. GEN6_OFFSET(0) |
  2614. GEN6_AGGRESSIVE_TURBO);
  2615. /* Make sure we continue to get interrupts
  2616. * until we hit the minimum or maximum frequencies.
  2617. */
  2618. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  2619. POSTING_READ(GEN6_RPNSWREQ);
  2620. dev_priv->rps.cur_delay = val;
  2621. trace_intel_gpu_freq_change(val * 50);
  2622. }
  2623. void valleyview_set_rps(struct drm_device *dev, u8 val)
  2624. {
  2625. struct drm_i915_private *dev_priv = dev->dev_private;
  2626. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  2627. u32 limits = gen6_rps_limits(dev_priv, &val);
  2628. u32 pval;
  2629. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2630. WARN_ON(val > dev_priv->rps.max_delay);
  2631. WARN_ON(val < dev_priv->rps.min_delay);
  2632. DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
  2633. vlv_gpu_freq(dev_priv->mem_freq,
  2634. dev_priv->rps.cur_delay),
  2635. vlv_gpu_freq(dev_priv->mem_freq, val));
  2636. if (val == dev_priv->rps.cur_delay)
  2637. return;
  2638. vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
  2639. do {
  2640. pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  2641. if (time_after(jiffies, timeout)) {
  2642. DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
  2643. break;
  2644. }
  2645. udelay(10);
  2646. } while (pval & 1);
  2647. pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  2648. if ((pval >> 8) != val)
  2649. DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
  2650. val, pval >> 8);
  2651. /* Make sure we continue to get interrupts
  2652. * until we hit the minimum or maximum frequencies.
  2653. */
  2654. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
  2655. dev_priv->rps.cur_delay = pval >> 8;
  2656. trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
  2657. }
  2658. static void gen6_disable_rps(struct drm_device *dev)
  2659. {
  2660. struct drm_i915_private *dev_priv = dev->dev_private;
  2661. I915_WRITE(GEN6_RC_CONTROL, 0);
  2662. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  2663. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  2664. I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
  2665. /* Complete PM interrupt masking here doesn't race with the rps work
  2666. * item again unmasking PM interrupts because that is using a different
  2667. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  2668. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  2669. spin_lock_irq(&dev_priv->rps.lock);
  2670. dev_priv->rps.pm_iir = 0;
  2671. spin_unlock_irq(&dev_priv->rps.lock);
  2672. I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
  2673. }
  2674. static void valleyview_disable_rps(struct drm_device *dev)
  2675. {
  2676. struct drm_i915_private *dev_priv = dev->dev_private;
  2677. I915_WRITE(GEN6_RC_CONTROL, 0);
  2678. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  2679. I915_WRITE(GEN6_PMIER, 0);
  2680. /* Complete PM interrupt masking here doesn't race with the rps work
  2681. * item again unmasking PM interrupts because that is using a different
  2682. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  2683. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  2684. spin_lock_irq(&dev_priv->rps.lock);
  2685. dev_priv->rps.pm_iir = 0;
  2686. spin_unlock_irq(&dev_priv->rps.lock);
  2687. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  2688. if (dev_priv->vlv_pctx) {
  2689. drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
  2690. dev_priv->vlv_pctx = NULL;
  2691. }
  2692. }
  2693. int intel_enable_rc6(const struct drm_device *dev)
  2694. {
  2695. /* Respect the kernel parameter if it is set */
  2696. if (i915_enable_rc6 >= 0)
  2697. return i915_enable_rc6;
  2698. /* Disable RC6 on Ironlake */
  2699. if (INTEL_INFO(dev)->gen == 5)
  2700. return 0;
  2701. if (IS_HASWELL(dev)) {
  2702. DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
  2703. return INTEL_RC6_ENABLE;
  2704. }
  2705. /* snb/ivb have more than one rc6 state. */
  2706. if (INTEL_INFO(dev)->gen == 6) {
  2707. DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
  2708. return INTEL_RC6_ENABLE;
  2709. }
  2710. DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
  2711. return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
  2712. }
  2713. static void gen6_enable_rps(struct drm_device *dev)
  2714. {
  2715. struct drm_i915_private *dev_priv = dev->dev_private;
  2716. struct intel_ring_buffer *ring;
  2717. u32 rp_state_cap;
  2718. u32 gt_perf_status;
  2719. u32 rc6vids, pcu_mbox, rc6_mask = 0;
  2720. u32 gtfifodbg;
  2721. int rc6_mode;
  2722. int i, ret;
  2723. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2724. /* Here begins a magic sequence of register writes to enable
  2725. * auto-downclocking.
  2726. *
  2727. * Perhaps there might be some value in exposing these to
  2728. * userspace...
  2729. */
  2730. I915_WRITE(GEN6_RC_STATE, 0);
  2731. /* Clear the DBG now so we don't confuse earlier errors */
  2732. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  2733. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  2734. I915_WRITE(GTFIFODBG, gtfifodbg);
  2735. }
  2736. gen6_gt_force_wake_get(dev_priv);
  2737. rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  2738. gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  2739. /* In units of 50MHz */
  2740. dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
  2741. dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
  2742. dev_priv->rps.cur_delay = 0;
  2743. /* disable the counters and set deterministic thresholds */
  2744. I915_WRITE(GEN6_RC_CONTROL, 0);
  2745. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  2746. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  2747. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  2748. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  2749. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  2750. for_each_ring(ring, dev_priv, i)
  2751. I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  2752. I915_WRITE(GEN6_RC_SLEEP, 0);
  2753. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  2754. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  2755. I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
  2756. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  2757. /* Check if we are enabling RC6 */
  2758. rc6_mode = intel_enable_rc6(dev_priv->dev);
  2759. if (rc6_mode & INTEL_RC6_ENABLE)
  2760. rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
  2761. /* We don't use those on Haswell */
  2762. if (!IS_HASWELL(dev)) {
  2763. if (rc6_mode & INTEL_RC6p_ENABLE)
  2764. rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
  2765. if (rc6_mode & INTEL_RC6pp_ENABLE)
  2766. rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
  2767. }
  2768. DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
  2769. (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
  2770. (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
  2771. (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
  2772. I915_WRITE(GEN6_RC_CONTROL,
  2773. rc6_mask |
  2774. GEN6_RC_CTL_EI_MODE(1) |
  2775. GEN6_RC_CTL_HW_ENABLE);
  2776. if (IS_HASWELL(dev)) {
  2777. I915_WRITE(GEN6_RPNSWREQ,
  2778. HSW_FREQUENCY(10));
  2779. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2780. HSW_FREQUENCY(12));
  2781. } else {
  2782. I915_WRITE(GEN6_RPNSWREQ,
  2783. GEN6_FREQUENCY(10) |
  2784. GEN6_OFFSET(0) |
  2785. GEN6_AGGRESSIVE_TURBO);
  2786. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  2787. GEN6_FREQUENCY(12));
  2788. }
  2789. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  2790. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  2791. dev_priv->rps.max_delay << 24 |
  2792. dev_priv->rps.min_delay << 16);
  2793. I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  2794. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  2795. I915_WRITE(GEN6_RP_UP_EI, 66000);
  2796. I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  2797. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2798. I915_WRITE(GEN6_RP_CONTROL,
  2799. GEN6_RP_MEDIA_TURBO |
  2800. GEN6_RP_MEDIA_HW_NORMAL_MODE |
  2801. GEN6_RP_MEDIA_IS_GFX |
  2802. GEN6_RP_ENABLE |
  2803. GEN6_RP_UP_BUSY_AVG |
  2804. (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
  2805. ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
  2806. if (!ret) {
  2807. pcu_mbox = 0;
  2808. ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
  2809. if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
  2810. DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
  2811. (dev_priv->rps.max_delay & 0xff) * 50,
  2812. (pcu_mbox & 0xff) * 50);
  2813. dev_priv->rps.hw_max = pcu_mbox & 0xff;
  2814. }
  2815. } else {
  2816. DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
  2817. }
  2818. gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
  2819. /* requires MSI enabled */
  2820. I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
  2821. spin_lock_irq(&dev_priv->rps.lock);
  2822. /* FIXME: Our interrupt enabling sequence is bonghits.
  2823. * dev_priv->rps.pm_iir really should be 0 here. */
  2824. dev_priv->rps.pm_iir = 0;
  2825. I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
  2826. I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
  2827. spin_unlock_irq(&dev_priv->rps.lock);
  2828. /* unmask all PM interrupts */
  2829. I915_WRITE(GEN6_PMINTRMSK, 0);
  2830. rc6vids = 0;
  2831. ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
  2832. if (IS_GEN6(dev) && ret) {
  2833. DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
  2834. } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
  2835. DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
  2836. GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
  2837. rc6vids &= 0xffff00;
  2838. rc6vids |= GEN6_ENCODE_RC6_VID(450);
  2839. ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
  2840. if (ret)
  2841. DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
  2842. }
  2843. gen6_gt_force_wake_put(dev_priv);
  2844. }
  2845. static void gen6_update_ring_freq(struct drm_device *dev)
  2846. {
  2847. struct drm_i915_private *dev_priv = dev->dev_private;
  2848. int min_freq = 15;
  2849. unsigned int gpu_freq;
  2850. unsigned int max_ia_freq, min_ring_freq;
  2851. int scaling_factor = 180;
  2852. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2853. max_ia_freq = cpufreq_quick_get_max(0);
  2854. /*
  2855. * Default to measured freq if none found, PCU will ensure we don't go
  2856. * over
  2857. */
  2858. if (!max_ia_freq)
  2859. max_ia_freq = tsc_khz;
  2860. /* Convert from kHz to MHz */
  2861. max_ia_freq /= 1000;
  2862. min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
  2863. /* convert DDR frequency from units of 133.3MHz to bandwidth */
  2864. min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
  2865. /*
  2866. * For each potential GPU frequency, load a ring frequency we'd like
  2867. * to use for memory access. We do this by specifying the IA frequency
  2868. * the PCU should use as a reference to determine the ring frequency.
  2869. */
  2870. for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
  2871. gpu_freq--) {
  2872. int diff = dev_priv->rps.max_delay - gpu_freq;
  2873. unsigned int ia_freq = 0, ring_freq = 0;
  2874. if (IS_HASWELL(dev)) {
  2875. ring_freq = (gpu_freq * 5 + 3) / 4;
  2876. ring_freq = max(min_ring_freq, ring_freq);
  2877. /* leave ia_freq as the default, chosen by cpufreq */
  2878. } else {
  2879. /* On older processors, there is no separate ring
  2880. * clock domain, so in order to boost the bandwidth
  2881. * of the ring, we need to upclock the CPU (ia_freq).
  2882. *
  2883. * For GPU frequencies less than 750MHz,
  2884. * just use the lowest ring freq.
  2885. */
  2886. if (gpu_freq < min_freq)
  2887. ia_freq = 800;
  2888. else
  2889. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  2890. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  2891. }
  2892. sandybridge_pcode_write(dev_priv,
  2893. GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
  2894. ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
  2895. ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
  2896. gpu_freq);
  2897. }
  2898. }
  2899. int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
  2900. {
  2901. u32 val, rp0;
  2902. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
  2903. rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
  2904. /* Clamp to max */
  2905. rp0 = min_t(u32, rp0, 0xea);
  2906. return rp0;
  2907. }
  2908. static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
  2909. {
  2910. u32 val, rpe;
  2911. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
  2912. rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
  2913. val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
  2914. rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
  2915. return rpe;
  2916. }
  2917. int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
  2918. {
  2919. return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
  2920. }
  2921. static void vlv_rps_timer_work(struct work_struct *work)
  2922. {
  2923. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  2924. rps.vlv_work.work);
  2925. /*
  2926. * Timer fired, we must be idle. Drop to min voltage state.
  2927. * Note: we use RPe here since it should match the
  2928. * Vmin we were shooting for. That should give us better
  2929. * perf when we come back out of RC6 than if we used the
  2930. * min freq available.
  2931. */
  2932. mutex_lock(&dev_priv->rps.hw_lock);
  2933. valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
  2934. mutex_unlock(&dev_priv->rps.hw_lock);
  2935. }
  2936. static void valleyview_setup_pctx(struct drm_device *dev)
  2937. {
  2938. struct drm_i915_private *dev_priv = dev->dev_private;
  2939. struct drm_i915_gem_object *pctx;
  2940. unsigned long pctx_paddr;
  2941. u32 pcbr;
  2942. int pctx_size = 24*1024;
  2943. pcbr = I915_READ(VLV_PCBR);
  2944. if (pcbr) {
  2945. /* BIOS set it up already, grab the pre-alloc'd space */
  2946. int pcbr_offset;
  2947. pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
  2948. pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
  2949. pcbr_offset,
  2950. -1,
  2951. pctx_size);
  2952. goto out;
  2953. }
  2954. /*
  2955. * From the Gunit register HAS:
  2956. * The Gfx driver is expected to program this register and ensure
  2957. * proper allocation within Gfx stolen memory. For example, this
  2958. * register should be programmed such than the PCBR range does not
  2959. * overlap with other ranges, such as the frame buffer, protected
  2960. * memory, or any other relevant ranges.
  2961. */
  2962. pctx = i915_gem_object_create_stolen(dev, pctx_size);
  2963. if (!pctx) {
  2964. DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
  2965. return;
  2966. }
  2967. pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
  2968. I915_WRITE(VLV_PCBR, pctx_paddr);
  2969. out:
  2970. dev_priv->vlv_pctx = pctx;
  2971. }
  2972. static void valleyview_enable_rps(struct drm_device *dev)
  2973. {
  2974. struct drm_i915_private *dev_priv = dev->dev_private;
  2975. struct intel_ring_buffer *ring;
  2976. u32 gtfifodbg, val, rpe;
  2977. int i;
  2978. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  2979. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  2980. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  2981. I915_WRITE(GTFIFODBG, gtfifodbg);
  2982. }
  2983. valleyview_setup_pctx(dev);
  2984. gen6_gt_force_wake_get(dev_priv);
  2985. I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
  2986. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
  2987. I915_WRITE(GEN6_RP_UP_EI, 66000);
  2988. I915_WRITE(GEN6_RP_DOWN_EI, 350000);
  2989. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  2990. I915_WRITE(GEN6_RP_CONTROL,
  2991. GEN6_RP_MEDIA_TURBO |
  2992. GEN6_RP_MEDIA_HW_NORMAL_MODE |
  2993. GEN6_RP_MEDIA_IS_GFX |
  2994. GEN6_RP_ENABLE |
  2995. GEN6_RP_UP_BUSY_AVG |
  2996. GEN6_RP_DOWN_IDLE_CONT);
  2997. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
  2998. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  2999. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  3000. for_each_ring(ring, dev_priv, i)
  3001. I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
  3002. I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
  3003. /* allows RC6 residency counter to work */
  3004. I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
  3005. I915_WRITE(GEN6_RC_CONTROL,
  3006. GEN7_RC_CTL_TO_MODE);
  3007. val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
  3008. switch ((val >> 6) & 3) {
  3009. case 0:
  3010. case 1:
  3011. dev_priv->mem_freq = 800;
  3012. break;
  3013. case 2:
  3014. dev_priv->mem_freq = 1066;
  3015. break;
  3016. case 3:
  3017. dev_priv->mem_freq = 1333;
  3018. break;
  3019. }
  3020. DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
  3021. DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
  3022. DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
  3023. DRM_DEBUG_DRIVER("current GPU freq: %d\n",
  3024. vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
  3025. dev_priv->rps.cur_delay = (val >> 8) & 0xff;
  3026. dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
  3027. dev_priv->rps.hw_max = dev_priv->rps.max_delay;
  3028. DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
  3029. dev_priv->rps.max_delay));
  3030. rpe = valleyview_rps_rpe_freq(dev_priv);
  3031. DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
  3032. vlv_gpu_freq(dev_priv->mem_freq, rpe));
  3033. dev_priv->rps.rpe_delay = rpe;
  3034. val = valleyview_rps_min_freq(dev_priv);
  3035. DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
  3036. val));
  3037. dev_priv->rps.min_delay = val;
  3038. DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
  3039. vlv_gpu_freq(dev_priv->mem_freq, rpe));
  3040. INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
  3041. valleyview_set_rps(dev_priv->dev, rpe);
  3042. /* requires MSI enabled */
  3043. I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
  3044. spin_lock_irq(&dev_priv->rps.lock);
  3045. WARN_ON(dev_priv->rps.pm_iir != 0);
  3046. I915_WRITE(GEN6_PMIMR, 0);
  3047. spin_unlock_irq(&dev_priv->rps.lock);
  3048. /* enable all PM interrupts */
  3049. I915_WRITE(GEN6_PMINTRMSK, 0);
  3050. gen6_gt_force_wake_put(dev_priv);
  3051. }
  3052. void ironlake_teardown_rc6(struct drm_device *dev)
  3053. {
  3054. struct drm_i915_private *dev_priv = dev->dev_private;
  3055. if (dev_priv->ips.renderctx) {
  3056. i915_gem_object_unpin(dev_priv->ips.renderctx);
  3057. drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
  3058. dev_priv->ips.renderctx = NULL;
  3059. }
  3060. if (dev_priv->ips.pwrctx) {
  3061. i915_gem_object_unpin(dev_priv->ips.pwrctx);
  3062. drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
  3063. dev_priv->ips.pwrctx = NULL;
  3064. }
  3065. }
  3066. static void ironlake_disable_rc6(struct drm_device *dev)
  3067. {
  3068. struct drm_i915_private *dev_priv = dev->dev_private;
  3069. if (I915_READ(PWRCTXA)) {
  3070. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  3071. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  3072. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  3073. 50);
  3074. I915_WRITE(PWRCTXA, 0);
  3075. POSTING_READ(PWRCTXA);
  3076. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  3077. POSTING_READ(RSTDBYCTL);
  3078. }
  3079. }
  3080. static int ironlake_setup_rc6(struct drm_device *dev)
  3081. {
  3082. struct drm_i915_private *dev_priv = dev->dev_private;
  3083. if (dev_priv->ips.renderctx == NULL)
  3084. dev_priv->ips.renderctx = intel_alloc_context_page(dev);
  3085. if (!dev_priv->ips.renderctx)
  3086. return -ENOMEM;
  3087. if (dev_priv->ips.pwrctx == NULL)
  3088. dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
  3089. if (!dev_priv->ips.pwrctx) {
  3090. ironlake_teardown_rc6(dev);
  3091. return -ENOMEM;
  3092. }
  3093. return 0;
  3094. }
  3095. static void ironlake_enable_rc6(struct drm_device *dev)
  3096. {
  3097. struct drm_i915_private *dev_priv = dev->dev_private;
  3098. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  3099. bool was_interruptible;
  3100. int ret;
  3101. /* rc6 disabled by default due to repeated reports of hanging during
  3102. * boot and resume.
  3103. */
  3104. if (!intel_enable_rc6(dev))
  3105. return;
  3106. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  3107. ret = ironlake_setup_rc6(dev);
  3108. if (ret)
  3109. return;
  3110. was_interruptible = dev_priv->mm.interruptible;
  3111. dev_priv->mm.interruptible = false;
  3112. /*
  3113. * GPU can automatically power down the render unit if given a page
  3114. * to save state.
  3115. */
  3116. ret = intel_ring_begin(ring, 6);
  3117. if (ret) {
  3118. ironlake_teardown_rc6(dev);
  3119. dev_priv->mm.interruptible = was_interruptible;
  3120. return;
  3121. }
  3122. intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  3123. intel_ring_emit(ring, MI_SET_CONTEXT);
  3124. intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
  3125. MI_MM_SPACE_GTT |
  3126. MI_SAVE_EXT_STATE_EN |
  3127. MI_RESTORE_EXT_STATE_EN |
  3128. MI_RESTORE_INHIBIT);
  3129. intel_ring_emit(ring, MI_SUSPEND_FLUSH);
  3130. intel_ring_emit(ring, MI_NOOP);
  3131. intel_ring_emit(ring, MI_FLUSH);
  3132. intel_ring_advance(ring);
  3133. /*
  3134. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  3135. * does an implicit flush, combined with MI_FLUSH above, it should be
  3136. * safe to assume that renderctx is valid
  3137. */
  3138. ret = intel_ring_idle(ring);
  3139. dev_priv->mm.interruptible = was_interruptible;
  3140. if (ret) {
  3141. DRM_ERROR("failed to enable ironlake power savings\n");
  3142. ironlake_teardown_rc6(dev);
  3143. return;
  3144. }
  3145. I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
  3146. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  3147. }
  3148. static unsigned long intel_pxfreq(u32 vidfreq)
  3149. {
  3150. unsigned long freq;
  3151. int div = (vidfreq & 0x3f0000) >> 16;
  3152. int post = (vidfreq & 0x3000) >> 12;
  3153. int pre = (vidfreq & 0x7);
  3154. if (!pre)
  3155. return 0;
  3156. freq = ((div * 133333) / ((1<<post) * pre));
  3157. return freq;
  3158. }
  3159. static const struct cparams {
  3160. u16 i;
  3161. u16 t;
  3162. u16 m;
  3163. u16 c;
  3164. } cparams[] = {
  3165. { 1, 1333, 301, 28664 },
  3166. { 1, 1066, 294, 24460 },
  3167. { 1, 800, 294, 25192 },
  3168. { 0, 1333, 276, 27605 },
  3169. { 0, 1066, 276, 27605 },
  3170. { 0, 800, 231, 23784 },
  3171. };
  3172. static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
  3173. {
  3174. u64 total_count, diff, ret;
  3175. u32 count1, count2, count3, m = 0, c = 0;
  3176. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  3177. int i;
  3178. assert_spin_locked(&mchdev_lock);
  3179. diff1 = now - dev_priv->ips.last_time1;
  3180. /* Prevent division-by-zero if we are asking too fast.
  3181. * Also, we don't get interesting results if we are polling
  3182. * faster than once in 10ms, so just return the saved value
  3183. * in such cases.
  3184. */
  3185. if (diff1 <= 10)
  3186. return dev_priv->ips.chipset_power;
  3187. count1 = I915_READ(DMIEC);
  3188. count2 = I915_READ(DDREC);
  3189. count3 = I915_READ(CSIEC);
  3190. total_count = count1 + count2 + count3;
  3191. /* FIXME: handle per-counter overflow */
  3192. if (total_count < dev_priv->ips.last_count1) {
  3193. diff = ~0UL - dev_priv->ips.last_count1;
  3194. diff += total_count;
  3195. } else {
  3196. diff = total_count - dev_priv->ips.last_count1;
  3197. }
  3198. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  3199. if (cparams[i].i == dev_priv->ips.c_m &&
  3200. cparams[i].t == dev_priv->ips.r_t) {
  3201. m = cparams[i].m;
  3202. c = cparams[i].c;
  3203. break;
  3204. }
  3205. }
  3206. diff = div_u64(diff, diff1);
  3207. ret = ((m * diff) + c);
  3208. ret = div_u64(ret, 10);
  3209. dev_priv->ips.last_count1 = total_count;
  3210. dev_priv->ips.last_time1 = now;
  3211. dev_priv->ips.chipset_power = ret;
  3212. return ret;
  3213. }
  3214. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  3215. {
  3216. unsigned long val;
  3217. if (dev_priv->info->gen != 5)
  3218. return 0;
  3219. spin_lock_irq(&mchdev_lock);
  3220. val = __i915_chipset_val(dev_priv);
  3221. spin_unlock_irq(&mchdev_lock);
  3222. return val;
  3223. }
  3224. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  3225. {
  3226. unsigned long m, x, b;
  3227. u32 tsfs;
  3228. tsfs = I915_READ(TSFS);
  3229. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  3230. x = I915_READ8(TR1);
  3231. b = tsfs & TSFS_INTR_MASK;
  3232. return ((m * x) / 127) - b;
  3233. }
  3234. static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  3235. {
  3236. static const struct v_table {
  3237. u16 vd; /* in .1 mil */
  3238. u16 vm; /* in .1 mil */
  3239. } v_table[] = {
  3240. { 0, 0, },
  3241. { 375, 0, },
  3242. { 500, 0, },
  3243. { 625, 0, },
  3244. { 750, 0, },
  3245. { 875, 0, },
  3246. { 1000, 0, },
  3247. { 1125, 0, },
  3248. { 4125, 3000, },
  3249. { 4125, 3000, },
  3250. { 4125, 3000, },
  3251. { 4125, 3000, },
  3252. { 4125, 3000, },
  3253. { 4125, 3000, },
  3254. { 4125, 3000, },
  3255. { 4125, 3000, },
  3256. { 4125, 3000, },
  3257. { 4125, 3000, },
  3258. { 4125, 3000, },
  3259. { 4125, 3000, },
  3260. { 4125, 3000, },
  3261. { 4125, 3000, },
  3262. { 4125, 3000, },
  3263. { 4125, 3000, },
  3264. { 4125, 3000, },
  3265. { 4125, 3000, },
  3266. { 4125, 3000, },
  3267. { 4125, 3000, },
  3268. { 4125, 3000, },
  3269. { 4125, 3000, },
  3270. { 4125, 3000, },
  3271. { 4125, 3000, },
  3272. { 4250, 3125, },
  3273. { 4375, 3250, },
  3274. { 4500, 3375, },
  3275. { 4625, 3500, },
  3276. { 4750, 3625, },
  3277. { 4875, 3750, },
  3278. { 5000, 3875, },
  3279. { 5125, 4000, },
  3280. { 5250, 4125, },
  3281. { 5375, 4250, },
  3282. { 5500, 4375, },
  3283. { 5625, 4500, },
  3284. { 5750, 4625, },
  3285. { 5875, 4750, },
  3286. { 6000, 4875, },
  3287. { 6125, 5000, },
  3288. { 6250, 5125, },
  3289. { 6375, 5250, },
  3290. { 6500, 5375, },
  3291. { 6625, 5500, },
  3292. { 6750, 5625, },
  3293. { 6875, 5750, },
  3294. { 7000, 5875, },
  3295. { 7125, 6000, },
  3296. { 7250, 6125, },
  3297. { 7375, 6250, },
  3298. { 7500, 6375, },
  3299. { 7625, 6500, },
  3300. { 7750, 6625, },
  3301. { 7875, 6750, },
  3302. { 8000, 6875, },
  3303. { 8125, 7000, },
  3304. { 8250, 7125, },
  3305. { 8375, 7250, },
  3306. { 8500, 7375, },
  3307. { 8625, 7500, },
  3308. { 8750, 7625, },
  3309. { 8875, 7750, },
  3310. { 9000, 7875, },
  3311. { 9125, 8000, },
  3312. { 9250, 8125, },
  3313. { 9375, 8250, },
  3314. { 9500, 8375, },
  3315. { 9625, 8500, },
  3316. { 9750, 8625, },
  3317. { 9875, 8750, },
  3318. { 10000, 8875, },
  3319. { 10125, 9000, },
  3320. { 10250, 9125, },
  3321. { 10375, 9250, },
  3322. { 10500, 9375, },
  3323. { 10625, 9500, },
  3324. { 10750, 9625, },
  3325. { 10875, 9750, },
  3326. { 11000, 9875, },
  3327. { 11125, 10000, },
  3328. { 11250, 10125, },
  3329. { 11375, 10250, },
  3330. { 11500, 10375, },
  3331. { 11625, 10500, },
  3332. { 11750, 10625, },
  3333. { 11875, 10750, },
  3334. { 12000, 10875, },
  3335. { 12125, 11000, },
  3336. { 12250, 11125, },
  3337. { 12375, 11250, },
  3338. { 12500, 11375, },
  3339. { 12625, 11500, },
  3340. { 12750, 11625, },
  3341. { 12875, 11750, },
  3342. { 13000, 11875, },
  3343. { 13125, 12000, },
  3344. { 13250, 12125, },
  3345. { 13375, 12250, },
  3346. { 13500, 12375, },
  3347. { 13625, 12500, },
  3348. { 13750, 12625, },
  3349. { 13875, 12750, },
  3350. { 14000, 12875, },
  3351. { 14125, 13000, },
  3352. { 14250, 13125, },
  3353. { 14375, 13250, },
  3354. { 14500, 13375, },
  3355. { 14625, 13500, },
  3356. { 14750, 13625, },
  3357. { 14875, 13750, },
  3358. { 15000, 13875, },
  3359. { 15125, 14000, },
  3360. { 15250, 14125, },
  3361. { 15375, 14250, },
  3362. { 15500, 14375, },
  3363. { 15625, 14500, },
  3364. { 15750, 14625, },
  3365. { 15875, 14750, },
  3366. { 16000, 14875, },
  3367. { 16125, 15000, },
  3368. };
  3369. if (dev_priv->info->is_mobile)
  3370. return v_table[pxvid].vm;
  3371. else
  3372. return v_table[pxvid].vd;
  3373. }
  3374. static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
  3375. {
  3376. struct timespec now, diff1;
  3377. u64 diff;
  3378. unsigned long diffms;
  3379. u32 count;
  3380. assert_spin_locked(&mchdev_lock);
  3381. getrawmonotonic(&now);
  3382. diff1 = timespec_sub(now, dev_priv->ips.last_time2);
  3383. /* Don't divide by 0 */
  3384. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  3385. if (!diffms)
  3386. return;
  3387. count = I915_READ(GFXEC);
  3388. if (count < dev_priv->ips.last_count2) {
  3389. diff = ~0UL - dev_priv->ips.last_count2;
  3390. diff += count;
  3391. } else {
  3392. diff = count - dev_priv->ips.last_count2;
  3393. }
  3394. dev_priv->ips.last_count2 = count;
  3395. dev_priv->ips.last_time2 = now;
  3396. /* More magic constants... */
  3397. diff = diff * 1181;
  3398. diff = div_u64(diff, diffms * 10);
  3399. dev_priv->ips.gfx_power = diff;
  3400. }
  3401. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  3402. {
  3403. if (dev_priv->info->gen != 5)
  3404. return;
  3405. spin_lock_irq(&mchdev_lock);
  3406. __i915_update_gfx_val(dev_priv);
  3407. spin_unlock_irq(&mchdev_lock);
  3408. }
  3409. static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
  3410. {
  3411. unsigned long t, corr, state1, corr2, state2;
  3412. u32 pxvid, ext_v;
  3413. assert_spin_locked(&mchdev_lock);
  3414. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
  3415. pxvid = (pxvid >> 24) & 0x7f;
  3416. ext_v = pvid_to_extvid(dev_priv, pxvid);
  3417. state1 = ext_v;
  3418. t = i915_mch_val(dev_priv);
  3419. /* Revel in the empirically derived constants */
  3420. /* Correction factor in 1/100000 units */
  3421. if (t > 80)
  3422. corr = ((t * 2349) + 135940);
  3423. else if (t >= 50)
  3424. corr = ((t * 964) + 29317);
  3425. else /* < 50 */
  3426. corr = ((t * 301) + 1004);
  3427. corr = corr * ((150142 * state1) / 10000 - 78642);
  3428. corr /= 100000;
  3429. corr2 = (corr * dev_priv->ips.corr);
  3430. state2 = (corr2 * state1) / 10000;
  3431. state2 /= 100; /* convert to mW */
  3432. __i915_update_gfx_val(dev_priv);
  3433. return dev_priv->ips.gfx_power + state2;
  3434. }
  3435. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  3436. {
  3437. unsigned long val;
  3438. if (dev_priv->info->gen != 5)
  3439. return 0;
  3440. spin_lock_irq(&mchdev_lock);
  3441. val = __i915_gfx_val(dev_priv);
  3442. spin_unlock_irq(&mchdev_lock);
  3443. return val;
  3444. }
  3445. /**
  3446. * i915_read_mch_val - return value for IPS use
  3447. *
  3448. * Calculate and return a value for the IPS driver to use when deciding whether
  3449. * we have thermal and power headroom to increase CPU or GPU power budget.
  3450. */
  3451. unsigned long i915_read_mch_val(void)
  3452. {
  3453. struct drm_i915_private *dev_priv;
  3454. unsigned long chipset_val, graphics_val, ret = 0;
  3455. spin_lock_irq(&mchdev_lock);
  3456. if (!i915_mch_dev)
  3457. goto out_unlock;
  3458. dev_priv = i915_mch_dev;
  3459. chipset_val = __i915_chipset_val(dev_priv);
  3460. graphics_val = __i915_gfx_val(dev_priv);
  3461. ret = chipset_val + graphics_val;
  3462. out_unlock:
  3463. spin_unlock_irq(&mchdev_lock);
  3464. return ret;
  3465. }
  3466. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  3467. /**
  3468. * i915_gpu_raise - raise GPU frequency limit
  3469. *
  3470. * Raise the limit; IPS indicates we have thermal headroom.
  3471. */
  3472. bool i915_gpu_raise(void)
  3473. {
  3474. struct drm_i915_private *dev_priv;
  3475. bool ret = true;
  3476. spin_lock_irq(&mchdev_lock);
  3477. if (!i915_mch_dev) {
  3478. ret = false;
  3479. goto out_unlock;
  3480. }
  3481. dev_priv = i915_mch_dev;
  3482. if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
  3483. dev_priv->ips.max_delay--;
  3484. out_unlock:
  3485. spin_unlock_irq(&mchdev_lock);
  3486. return ret;
  3487. }
  3488. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  3489. /**
  3490. * i915_gpu_lower - lower GPU frequency limit
  3491. *
  3492. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  3493. * frequency maximum.
  3494. */
  3495. bool i915_gpu_lower(void)
  3496. {
  3497. struct drm_i915_private *dev_priv;
  3498. bool ret = true;
  3499. spin_lock_irq(&mchdev_lock);
  3500. if (!i915_mch_dev) {
  3501. ret = false;
  3502. goto out_unlock;
  3503. }
  3504. dev_priv = i915_mch_dev;
  3505. if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
  3506. dev_priv->ips.max_delay++;
  3507. out_unlock:
  3508. spin_unlock_irq(&mchdev_lock);
  3509. return ret;
  3510. }
  3511. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  3512. /**
  3513. * i915_gpu_busy - indicate GPU business to IPS
  3514. *
  3515. * Tell the IPS driver whether or not the GPU is busy.
  3516. */
  3517. bool i915_gpu_busy(void)
  3518. {
  3519. struct drm_i915_private *dev_priv;
  3520. struct intel_ring_buffer *ring;
  3521. bool ret = false;
  3522. int i;
  3523. spin_lock_irq(&mchdev_lock);
  3524. if (!i915_mch_dev)
  3525. goto out_unlock;
  3526. dev_priv = i915_mch_dev;
  3527. for_each_ring(ring, dev_priv, i)
  3528. ret |= !list_empty(&ring->request_list);
  3529. out_unlock:
  3530. spin_unlock_irq(&mchdev_lock);
  3531. return ret;
  3532. }
  3533. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  3534. /**
  3535. * i915_gpu_turbo_disable - disable graphics turbo
  3536. *
  3537. * Disable graphics turbo by resetting the max frequency and setting the
  3538. * current frequency to the default.
  3539. */
  3540. bool i915_gpu_turbo_disable(void)
  3541. {
  3542. struct drm_i915_private *dev_priv;
  3543. bool ret = true;
  3544. spin_lock_irq(&mchdev_lock);
  3545. if (!i915_mch_dev) {
  3546. ret = false;
  3547. goto out_unlock;
  3548. }
  3549. dev_priv = i915_mch_dev;
  3550. dev_priv->ips.max_delay = dev_priv->ips.fstart;
  3551. if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
  3552. ret = false;
  3553. out_unlock:
  3554. spin_unlock_irq(&mchdev_lock);
  3555. return ret;
  3556. }
  3557. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  3558. /**
  3559. * Tells the intel_ips driver that the i915 driver is now loaded, if
  3560. * IPS got loaded first.
  3561. *
  3562. * This awkward dance is so that neither module has to depend on the
  3563. * other in order for IPS to do the appropriate communication of
  3564. * GPU turbo limits to i915.
  3565. */
  3566. static void
  3567. ips_ping_for_i915_load(void)
  3568. {
  3569. void (*link)(void);
  3570. link = symbol_get(ips_link_to_i915_driver);
  3571. if (link) {
  3572. link();
  3573. symbol_put(ips_link_to_i915_driver);
  3574. }
  3575. }
  3576. void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
  3577. {
  3578. /* We only register the i915 ips part with intel-ips once everything is
  3579. * set up, to avoid intel-ips sneaking in and reading bogus values. */
  3580. spin_lock_irq(&mchdev_lock);
  3581. i915_mch_dev = dev_priv;
  3582. spin_unlock_irq(&mchdev_lock);
  3583. ips_ping_for_i915_load();
  3584. }
  3585. void intel_gpu_ips_teardown(void)
  3586. {
  3587. spin_lock_irq(&mchdev_lock);
  3588. i915_mch_dev = NULL;
  3589. spin_unlock_irq(&mchdev_lock);
  3590. }
  3591. static void intel_init_emon(struct drm_device *dev)
  3592. {
  3593. struct drm_i915_private *dev_priv = dev->dev_private;
  3594. u32 lcfuse;
  3595. u8 pxw[16];
  3596. int i;
  3597. /* Disable to program */
  3598. I915_WRITE(ECR, 0);
  3599. POSTING_READ(ECR);
  3600. /* Program energy weights for various events */
  3601. I915_WRITE(SDEW, 0x15040d00);
  3602. I915_WRITE(CSIEW0, 0x007f0000);
  3603. I915_WRITE(CSIEW1, 0x1e220004);
  3604. I915_WRITE(CSIEW2, 0x04000004);
  3605. for (i = 0; i < 5; i++)
  3606. I915_WRITE(PEW + (i * 4), 0);
  3607. for (i = 0; i < 3; i++)
  3608. I915_WRITE(DEW + (i * 4), 0);
  3609. /* Program P-state weights to account for frequency power adjustment */
  3610. for (i = 0; i < 16; i++) {
  3611. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  3612. unsigned long freq = intel_pxfreq(pxvidfreq);
  3613. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  3614. PXVFREQ_PX_SHIFT;
  3615. unsigned long val;
  3616. val = vid * vid;
  3617. val *= (freq / 1000);
  3618. val *= 255;
  3619. val /= (127*127*900);
  3620. if (val > 0xff)
  3621. DRM_ERROR("bad pxval: %ld\n", val);
  3622. pxw[i] = val;
  3623. }
  3624. /* Render standby states get 0 weight */
  3625. pxw[14] = 0;
  3626. pxw[15] = 0;
  3627. for (i = 0; i < 4; i++) {
  3628. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  3629. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  3630. I915_WRITE(PXW + (i * 4), val);
  3631. }
  3632. /* Adjust magic regs to magic values (more experimental results) */
  3633. I915_WRITE(OGW0, 0);
  3634. I915_WRITE(OGW1, 0);
  3635. I915_WRITE(EG0, 0x00007f00);
  3636. I915_WRITE(EG1, 0x0000000e);
  3637. I915_WRITE(EG2, 0x000e0000);
  3638. I915_WRITE(EG3, 0x68000300);
  3639. I915_WRITE(EG4, 0x42000000);
  3640. I915_WRITE(EG5, 0x00140031);
  3641. I915_WRITE(EG6, 0);
  3642. I915_WRITE(EG7, 0);
  3643. for (i = 0; i < 8; i++)
  3644. I915_WRITE(PXWL + (i * 4), 0);
  3645. /* Enable PMON + select events */
  3646. I915_WRITE(ECR, 0x80000019);
  3647. lcfuse = I915_READ(LCFUSE02);
  3648. dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
  3649. }
  3650. void intel_disable_gt_powersave(struct drm_device *dev)
  3651. {
  3652. struct drm_i915_private *dev_priv = dev->dev_private;
  3653. /* Interrupts should be disabled already to avoid re-arming. */
  3654. WARN_ON(dev->irq_enabled);
  3655. if (IS_IRONLAKE_M(dev)) {
  3656. ironlake_disable_drps(dev);
  3657. ironlake_disable_rc6(dev);
  3658. } else if (INTEL_INFO(dev)->gen >= 6) {
  3659. cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
  3660. cancel_work_sync(&dev_priv->rps.work);
  3661. if (IS_VALLEYVIEW(dev))
  3662. cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
  3663. mutex_lock(&dev_priv->rps.hw_lock);
  3664. if (IS_VALLEYVIEW(dev))
  3665. valleyview_disable_rps(dev);
  3666. else
  3667. gen6_disable_rps(dev);
  3668. mutex_unlock(&dev_priv->rps.hw_lock);
  3669. }
  3670. }
  3671. static void intel_gen6_powersave_work(struct work_struct *work)
  3672. {
  3673. struct drm_i915_private *dev_priv =
  3674. container_of(work, struct drm_i915_private,
  3675. rps.delayed_resume_work.work);
  3676. struct drm_device *dev = dev_priv->dev;
  3677. mutex_lock(&dev_priv->rps.hw_lock);
  3678. if (IS_VALLEYVIEW(dev)) {
  3679. valleyview_enable_rps(dev);
  3680. } else {
  3681. gen6_enable_rps(dev);
  3682. gen6_update_ring_freq(dev);
  3683. }
  3684. mutex_unlock(&dev_priv->rps.hw_lock);
  3685. }
  3686. void intel_enable_gt_powersave(struct drm_device *dev)
  3687. {
  3688. struct drm_i915_private *dev_priv = dev->dev_private;
  3689. if (IS_IRONLAKE_M(dev)) {
  3690. ironlake_enable_drps(dev);
  3691. ironlake_enable_rc6(dev);
  3692. intel_init_emon(dev);
  3693. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  3694. /*
  3695. * PCU communication is slow and this doesn't need to be
  3696. * done at any specific time, so do this out of our fast path
  3697. * to make resume and init faster.
  3698. */
  3699. schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
  3700. round_jiffies_up_relative(HZ));
  3701. }
  3702. }
  3703. static void ibx_init_clock_gating(struct drm_device *dev)
  3704. {
  3705. struct drm_i915_private *dev_priv = dev->dev_private;
  3706. /*
  3707. * On Ibex Peak and Cougar Point, we need to disable clock
  3708. * gating for the panel power sequencer or it will fail to
  3709. * start up when no ports are active.
  3710. */
  3711. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3712. }
  3713. static void g4x_disable_trickle_feed(struct drm_device *dev)
  3714. {
  3715. struct drm_i915_private *dev_priv = dev->dev_private;
  3716. int pipe;
  3717. for_each_pipe(pipe) {
  3718. I915_WRITE(DSPCNTR(pipe),
  3719. I915_READ(DSPCNTR(pipe)) |
  3720. DISPPLANE_TRICKLE_FEED_DISABLE);
  3721. intel_flush_display_plane(dev_priv, pipe);
  3722. }
  3723. }
  3724. static void ironlake_init_clock_gating(struct drm_device *dev)
  3725. {
  3726. struct drm_i915_private *dev_priv = dev->dev_private;
  3727. uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
  3728. /* Required for FBC */
  3729. dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
  3730. ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
  3731. ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
  3732. I915_WRITE(PCH_3DCGDIS0,
  3733. MARIUNIT_CLOCK_GATE_DISABLE |
  3734. SVSMUNIT_CLOCK_GATE_DISABLE);
  3735. I915_WRITE(PCH_3DCGDIS1,
  3736. VFMUNIT_CLOCK_GATE_DISABLE);
  3737. /*
  3738. * According to the spec the following bits should be set in
  3739. * order to enable memory self-refresh
  3740. * The bit 22/21 of 0x42004
  3741. * The bit 5 of 0x42020
  3742. * The bit 15 of 0x45000
  3743. */
  3744. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3745. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  3746. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  3747. dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
  3748. I915_WRITE(DISP_ARB_CTL,
  3749. (I915_READ(DISP_ARB_CTL) |
  3750. DISP_FBC_WM_DIS));
  3751. I915_WRITE(WM3_LP_ILK, 0);
  3752. I915_WRITE(WM2_LP_ILK, 0);
  3753. I915_WRITE(WM1_LP_ILK, 0);
  3754. /*
  3755. * Based on the document from hardware guys the following bits
  3756. * should be set unconditionally in order to enable FBC.
  3757. * The bit 22 of 0x42000
  3758. * The bit 22 of 0x42004
  3759. * The bit 7,8,9 of 0x42020.
  3760. */
  3761. if (IS_IRONLAKE_M(dev)) {
  3762. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3763. I915_READ(ILK_DISPLAY_CHICKEN1) |
  3764. ILK_FBCQ_DIS);
  3765. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3766. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3767. ILK_DPARB_GATE);
  3768. }
  3769. I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
  3770. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3771. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3772. ILK_ELPIN_409_SELECT);
  3773. I915_WRITE(_3D_CHICKEN2,
  3774. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  3775. _3D_CHICKEN2_WM_READ_PIPELINED);
  3776. /* WaDisableRenderCachePipelinedFlush:ilk */
  3777. I915_WRITE(CACHE_MODE_0,
  3778. _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
  3779. g4x_disable_trickle_feed(dev);
  3780. ibx_init_clock_gating(dev);
  3781. }
  3782. static void cpt_init_clock_gating(struct drm_device *dev)
  3783. {
  3784. struct drm_i915_private *dev_priv = dev->dev_private;
  3785. int pipe;
  3786. uint32_t val;
  3787. /*
  3788. * On Ibex Peak and Cougar Point, we need to disable clock
  3789. * gating for the panel power sequencer or it will fail to
  3790. * start up when no ports are active.
  3791. */
  3792. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  3793. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  3794. DPLS_EDP_PPS_FIX_DIS);
  3795. /* The below fixes the weird display corruption, a few pixels shifted
  3796. * downward, on (only) LVDS of some HP laptops with IVY.
  3797. */
  3798. for_each_pipe(pipe) {
  3799. val = I915_READ(TRANS_CHICKEN2(pipe));
  3800. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  3801. val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
  3802. if (dev_priv->vbt.fdi_rx_polarity_inverted)
  3803. val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
  3804. val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
  3805. val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
  3806. val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
  3807. I915_WRITE(TRANS_CHICKEN2(pipe), val);
  3808. }
  3809. /* WADP0ClockGatingDisable */
  3810. for_each_pipe(pipe) {
  3811. I915_WRITE(TRANS_CHICKEN1(pipe),
  3812. TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
  3813. }
  3814. }
  3815. static void gen6_check_mch_setup(struct drm_device *dev)
  3816. {
  3817. struct drm_i915_private *dev_priv = dev->dev_private;
  3818. uint32_t tmp;
  3819. tmp = I915_READ(MCH_SSKPD);
  3820. if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
  3821. DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
  3822. DRM_INFO("This can cause pipe underruns and display issues.\n");
  3823. DRM_INFO("Please upgrade your BIOS to fix this.\n");
  3824. }
  3825. }
  3826. static void gen6_init_clock_gating(struct drm_device *dev)
  3827. {
  3828. struct drm_i915_private *dev_priv = dev->dev_private;
  3829. uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
  3830. I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
  3831. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3832. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3833. ILK_ELPIN_409_SELECT);
  3834. /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
  3835. I915_WRITE(_3D_CHICKEN,
  3836. _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
  3837. /* WaSetupGtModeTdRowDispatch:snb */
  3838. if (IS_SNB_GT1(dev))
  3839. I915_WRITE(GEN6_GT_MODE,
  3840. _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
  3841. I915_WRITE(WM3_LP_ILK, 0);
  3842. I915_WRITE(WM2_LP_ILK, 0);
  3843. I915_WRITE(WM1_LP_ILK, 0);
  3844. I915_WRITE(CACHE_MODE_0,
  3845. _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
  3846. I915_WRITE(GEN6_UCGCTL1,
  3847. I915_READ(GEN6_UCGCTL1) |
  3848. GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
  3849. GEN6_CSUNIT_CLOCK_GATE_DISABLE);
  3850. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  3851. * gating disable must be set. Failure to set it results in
  3852. * flickering pixels due to Z write ordering failures after
  3853. * some amount of runtime in the Mesa "fire" demo, and Unigine
  3854. * Sanctuary and Tropics, and apparently anything else with
  3855. * alpha test or pixel discard.
  3856. *
  3857. * According to the spec, bit 11 (RCCUNIT) must also be set,
  3858. * but we didn't debug actual testcases to find it out.
  3859. *
  3860. * Also apply WaDisableVDSUnitClockGating:snb and
  3861. * WaDisableRCPBUnitClockGating:snb.
  3862. */
  3863. I915_WRITE(GEN6_UCGCTL2,
  3864. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  3865. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  3866. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  3867. /* Bspec says we need to always set all mask bits. */
  3868. I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
  3869. _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
  3870. /*
  3871. * According to the spec the following bits should be
  3872. * set in order to enable memory self-refresh and fbc:
  3873. * The bit21 and bit22 of 0x42000
  3874. * The bit21 and bit22 of 0x42004
  3875. * The bit5 and bit7 of 0x42020
  3876. * The bit14 of 0x70180
  3877. * The bit14 of 0x71180
  3878. */
  3879. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  3880. I915_READ(ILK_DISPLAY_CHICKEN1) |
  3881. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  3882. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  3883. I915_READ(ILK_DISPLAY_CHICKEN2) |
  3884. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  3885. I915_WRITE(ILK_DSPCLK_GATE_D,
  3886. I915_READ(ILK_DSPCLK_GATE_D) |
  3887. ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
  3888. ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
  3889. /* WaMbcDriverBootEnable:snb */
  3890. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3891. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3892. g4x_disable_trickle_feed(dev);
  3893. /* The default value should be 0x200 according to docs, but the two
  3894. * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
  3895. I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
  3896. I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
  3897. cpt_init_clock_gating(dev);
  3898. gen6_check_mch_setup(dev);
  3899. }
  3900. static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
  3901. {
  3902. uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
  3903. reg &= ~GEN7_FF_SCHED_MASK;
  3904. reg |= GEN7_FF_TS_SCHED_HW;
  3905. reg |= GEN7_FF_VS_SCHED_HW;
  3906. reg |= GEN7_FF_DS_SCHED_HW;
  3907. if (IS_HASWELL(dev_priv->dev))
  3908. reg &= ~GEN7_FF_VS_REF_CNT_FFME;
  3909. I915_WRITE(GEN7_FF_THREAD_MODE, reg);
  3910. }
  3911. static void lpt_init_clock_gating(struct drm_device *dev)
  3912. {
  3913. struct drm_i915_private *dev_priv = dev->dev_private;
  3914. /*
  3915. * TODO: this bit should only be enabled when really needed, then
  3916. * disabled when not needed anymore in order to save power.
  3917. */
  3918. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
  3919. I915_WRITE(SOUTH_DSPCLK_GATE_D,
  3920. I915_READ(SOUTH_DSPCLK_GATE_D) |
  3921. PCH_LP_PARTITION_LEVEL_DISABLE);
  3922. /* WADPOClockGatingDisable:hsw */
  3923. I915_WRITE(_TRANSA_CHICKEN1,
  3924. I915_READ(_TRANSA_CHICKEN1) |
  3925. TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
  3926. }
  3927. static void lpt_suspend_hw(struct drm_device *dev)
  3928. {
  3929. struct drm_i915_private *dev_priv = dev->dev_private;
  3930. if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  3931. uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
  3932. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  3933. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  3934. }
  3935. }
  3936. static void haswell_init_clock_gating(struct drm_device *dev)
  3937. {
  3938. struct drm_i915_private *dev_priv = dev->dev_private;
  3939. I915_WRITE(WM3_LP_ILK, 0);
  3940. I915_WRITE(WM2_LP_ILK, 0);
  3941. I915_WRITE(WM1_LP_ILK, 0);
  3942. /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  3943. * This implements the WaDisableRCZUnitClockGating:hsw workaround.
  3944. */
  3945. I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
  3946. /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
  3947. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3948. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3949. /* WaApplyL3ControlAndL3ChickenMode:hsw */
  3950. I915_WRITE(GEN7_L3CNTLREG1,
  3951. GEN7_WA_FOR_GEN7_L3_CONTROL);
  3952. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  3953. GEN7_WA_L3_CHICKEN_MODE);
  3954. /* This is required by WaCatErrorRejectionIssue:hsw */
  3955. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  3956. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  3957. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  3958. g4x_disable_trickle_feed(dev);
  3959. /* WaVSRefCountFullforceMissDisable:hsw */
  3960. gen7_setup_fixed_func_scheduler(dev_priv);
  3961. /* WaDisable4x2SubspanOptimization:hsw */
  3962. I915_WRITE(CACHE_MODE_1,
  3963. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  3964. /* WaMbcDriverBootEnable:hsw */
  3965. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  3966. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  3967. /* WaSwitchSolVfFArbitrationPriority:hsw */
  3968. I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
  3969. /* WaRsPkgCStateDisplayPMReq:hsw */
  3970. I915_WRITE(CHICKEN_PAR1_1,
  3971. I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
  3972. lpt_init_clock_gating(dev);
  3973. }
  3974. static void ivybridge_init_clock_gating(struct drm_device *dev)
  3975. {
  3976. struct drm_i915_private *dev_priv = dev->dev_private;
  3977. uint32_t snpcr;
  3978. I915_WRITE(WM3_LP_ILK, 0);
  3979. I915_WRITE(WM2_LP_ILK, 0);
  3980. I915_WRITE(WM1_LP_ILK, 0);
  3981. I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
  3982. /* WaDisableEarlyCull:ivb */
  3983. I915_WRITE(_3D_CHICKEN3,
  3984. _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
  3985. /* WaDisableBackToBackFlipFix:ivb */
  3986. I915_WRITE(IVB_CHICKEN3,
  3987. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  3988. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  3989. /* WaDisablePSDDualDispatchEnable:ivb */
  3990. if (IS_IVB_GT1(dev))
  3991. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
  3992. _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  3993. else
  3994. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
  3995. _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  3996. /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
  3997. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  3998. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  3999. /* WaApplyL3ControlAndL3ChickenMode:ivb */
  4000. I915_WRITE(GEN7_L3CNTLREG1,
  4001. GEN7_WA_FOR_GEN7_L3_CONTROL);
  4002. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
  4003. GEN7_WA_L3_CHICKEN_MODE);
  4004. if (IS_IVB_GT1(dev))
  4005. I915_WRITE(GEN7_ROW_CHICKEN2,
  4006. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4007. else
  4008. I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
  4009. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4010. /* WaForceL3Serialization:ivb */
  4011. I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
  4012. ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
  4013. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  4014. * gating disable must be set. Failure to set it results in
  4015. * flickering pixels due to Z write ordering failures after
  4016. * some amount of runtime in the Mesa "fire" demo, and Unigine
  4017. * Sanctuary and Tropics, and apparently anything else with
  4018. * alpha test or pixel discard.
  4019. *
  4020. * According to the spec, bit 11 (RCCUNIT) must also be set,
  4021. * but we didn't debug actual testcases to find it out.
  4022. *
  4023. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  4024. * This implements the WaDisableRCZUnitClockGating:ivb workaround.
  4025. */
  4026. I915_WRITE(GEN6_UCGCTL2,
  4027. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  4028. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  4029. /* This is required by WaCatErrorRejectionIssue:ivb */
  4030. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  4031. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  4032. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  4033. g4x_disable_trickle_feed(dev);
  4034. /* WaMbcDriverBootEnable:ivb */
  4035. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4036. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4037. /* WaVSRefCountFullforceMissDisable:ivb */
  4038. gen7_setup_fixed_func_scheduler(dev_priv);
  4039. /* WaDisable4x2SubspanOptimization:ivb */
  4040. I915_WRITE(CACHE_MODE_1,
  4041. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  4042. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  4043. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  4044. snpcr |= GEN6_MBC_SNPCR_MED;
  4045. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  4046. if (!HAS_PCH_NOP(dev))
  4047. cpt_init_clock_gating(dev);
  4048. gen6_check_mch_setup(dev);
  4049. }
  4050. static void valleyview_init_clock_gating(struct drm_device *dev)
  4051. {
  4052. struct drm_i915_private *dev_priv = dev->dev_private;
  4053. I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
  4054. /* WaDisableEarlyCull:vlv */
  4055. I915_WRITE(_3D_CHICKEN3,
  4056. _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
  4057. /* WaDisableBackToBackFlipFix:vlv */
  4058. I915_WRITE(IVB_CHICKEN3,
  4059. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  4060. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  4061. /* WaDisablePSDDualDispatchEnable:vlv */
  4062. I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
  4063. _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
  4064. GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
  4065. /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
  4066. I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  4067. GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
  4068. /* WaApplyL3ControlAndL3ChickenMode:vlv */
  4069. I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
  4070. I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
  4071. /* WaForceL3Serialization:vlv */
  4072. I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
  4073. ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
  4074. /* WaDisableDopClockGating:vlv */
  4075. I915_WRITE(GEN7_ROW_CHICKEN2,
  4076. _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
  4077. /* WaForceL3Serialization:vlv */
  4078. I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
  4079. ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
  4080. /* This is required by WaCatErrorRejectionIssue:vlv */
  4081. I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
  4082. I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
  4083. GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
  4084. /* WaMbcDriverBootEnable:vlv */
  4085. I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
  4086. GEN6_MBCTL_ENABLE_BOOT_FETCH);
  4087. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  4088. * gating disable must be set. Failure to set it results in
  4089. * flickering pixels due to Z write ordering failures after
  4090. * some amount of runtime in the Mesa "fire" demo, and Unigine
  4091. * Sanctuary and Tropics, and apparently anything else with
  4092. * alpha test or pixel discard.
  4093. *
  4094. * According to the spec, bit 11 (RCCUNIT) must also be set,
  4095. * but we didn't debug actual testcases to find it out.
  4096. *
  4097. * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
  4098. * This implements the WaDisableRCZUnitClockGating:vlv workaround.
  4099. *
  4100. * Also apply WaDisableVDSUnitClockGating:vlv and
  4101. * WaDisableRCPBUnitClockGating:vlv.
  4102. */
  4103. I915_WRITE(GEN6_UCGCTL2,
  4104. GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
  4105. GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
  4106. GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
  4107. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  4108. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  4109. I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
  4110. I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
  4111. I915_WRITE(CACHE_MODE_1,
  4112. _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
  4113. /*
  4114. * WaDisableVLVClockGating_VBIIssue:vlv
  4115. * Disable clock gating on th GCFG unit to prevent a delay
  4116. * in the reporting of vblank events.
  4117. */
  4118. I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
  4119. /* Conservative clock gating settings for now */
  4120. I915_WRITE(0x9400, 0xffffffff);
  4121. I915_WRITE(0x9404, 0xffffffff);
  4122. I915_WRITE(0x9408, 0xffffffff);
  4123. I915_WRITE(0x940c, 0xffffffff);
  4124. I915_WRITE(0x9410, 0xffffffff);
  4125. I915_WRITE(0x9414, 0xffffffff);
  4126. I915_WRITE(0x9418, 0xffffffff);
  4127. }
  4128. static void g4x_init_clock_gating(struct drm_device *dev)
  4129. {
  4130. struct drm_i915_private *dev_priv = dev->dev_private;
  4131. uint32_t dspclk_gate;
  4132. I915_WRITE(RENCLK_GATE_D1, 0);
  4133. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4134. GS_UNIT_CLOCK_GATE_DISABLE |
  4135. CL_UNIT_CLOCK_GATE_DISABLE);
  4136. I915_WRITE(RAMCLK_GATE_D, 0);
  4137. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4138. OVRUNIT_CLOCK_GATE_DISABLE |
  4139. OVCUNIT_CLOCK_GATE_DISABLE;
  4140. if (IS_GM45(dev))
  4141. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4142. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4143. /* WaDisableRenderCachePipelinedFlush */
  4144. I915_WRITE(CACHE_MODE_0,
  4145. _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
  4146. g4x_disable_trickle_feed(dev);
  4147. }
  4148. static void crestline_init_clock_gating(struct drm_device *dev)
  4149. {
  4150. struct drm_i915_private *dev_priv = dev->dev_private;
  4151. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4152. I915_WRITE(RENCLK_GATE_D2, 0);
  4153. I915_WRITE(DSPCLK_GATE_D, 0);
  4154. I915_WRITE(RAMCLK_GATE_D, 0);
  4155. I915_WRITE16(DEUC, 0);
  4156. I915_WRITE(MI_ARB_STATE,
  4157. _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
  4158. }
  4159. static void broadwater_init_clock_gating(struct drm_device *dev)
  4160. {
  4161. struct drm_i915_private *dev_priv = dev->dev_private;
  4162. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4163. I965_RCC_CLOCK_GATE_DISABLE |
  4164. I965_RCPB_CLOCK_GATE_DISABLE |
  4165. I965_ISC_CLOCK_GATE_DISABLE |
  4166. I965_FBC_CLOCK_GATE_DISABLE);
  4167. I915_WRITE(RENCLK_GATE_D2, 0);
  4168. I915_WRITE(MI_ARB_STATE,
  4169. _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
  4170. }
  4171. static void gen3_init_clock_gating(struct drm_device *dev)
  4172. {
  4173. struct drm_i915_private *dev_priv = dev->dev_private;
  4174. u32 dstate = I915_READ(D_STATE);
  4175. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4176. DSTATE_DOT_CLOCK_GATING;
  4177. I915_WRITE(D_STATE, dstate);
  4178. if (IS_PINEVIEW(dev))
  4179. I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
  4180. /* IIR "flip pending" means done if this bit is set */
  4181. I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
  4182. }
  4183. static void i85x_init_clock_gating(struct drm_device *dev)
  4184. {
  4185. struct drm_i915_private *dev_priv = dev->dev_private;
  4186. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  4187. }
  4188. static void i830_init_clock_gating(struct drm_device *dev)
  4189. {
  4190. struct drm_i915_private *dev_priv = dev->dev_private;
  4191. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  4192. }
  4193. void intel_init_clock_gating(struct drm_device *dev)
  4194. {
  4195. struct drm_i915_private *dev_priv = dev->dev_private;
  4196. dev_priv->display.init_clock_gating(dev);
  4197. }
  4198. void intel_suspend_hw(struct drm_device *dev)
  4199. {
  4200. if (HAS_PCH_LPT(dev))
  4201. lpt_suspend_hw(dev);
  4202. }
  4203. /**
  4204. * We should only use the power well if we explicitly asked the hardware to
  4205. * enable it, so check if it's enabled and also check if we've requested it to
  4206. * be enabled.
  4207. */
  4208. bool intel_display_power_enabled(struct drm_device *dev,
  4209. enum intel_display_power_domain domain)
  4210. {
  4211. struct drm_i915_private *dev_priv = dev->dev_private;
  4212. if (!HAS_POWER_WELL(dev))
  4213. return true;
  4214. switch (domain) {
  4215. case POWER_DOMAIN_PIPE_A:
  4216. case POWER_DOMAIN_TRANSCODER_EDP:
  4217. return true;
  4218. case POWER_DOMAIN_PIPE_B:
  4219. case POWER_DOMAIN_PIPE_C:
  4220. case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  4221. case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  4222. case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  4223. case POWER_DOMAIN_TRANSCODER_A:
  4224. case POWER_DOMAIN_TRANSCODER_B:
  4225. case POWER_DOMAIN_TRANSCODER_C:
  4226. return I915_READ(HSW_PWR_WELL_DRIVER) ==
  4227. (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
  4228. default:
  4229. BUG();
  4230. }
  4231. }
  4232. static void __intel_set_power_well(struct drm_device *dev, bool enable)
  4233. {
  4234. struct drm_i915_private *dev_priv = dev->dev_private;
  4235. bool is_enabled, enable_requested;
  4236. uint32_t tmp;
  4237. tmp = I915_READ(HSW_PWR_WELL_DRIVER);
  4238. is_enabled = tmp & HSW_PWR_WELL_STATE;
  4239. enable_requested = tmp & HSW_PWR_WELL_ENABLE;
  4240. if (enable) {
  4241. if (!enable_requested)
  4242. I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
  4243. if (!is_enabled) {
  4244. DRM_DEBUG_KMS("Enabling power well\n");
  4245. if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
  4246. HSW_PWR_WELL_STATE), 20))
  4247. DRM_ERROR("Timeout enabling power well\n");
  4248. }
  4249. } else {
  4250. if (enable_requested) {
  4251. I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
  4252. DRM_DEBUG_KMS("Requesting to disable the power well\n");
  4253. }
  4254. }
  4255. }
  4256. static struct i915_power_well *hsw_pwr;
  4257. /* Display audio driver power well request */
  4258. void i915_request_power_well(void)
  4259. {
  4260. if (WARN_ON(!hsw_pwr))
  4261. return;
  4262. spin_lock_irq(&hsw_pwr->lock);
  4263. if (!hsw_pwr->count++ &&
  4264. !hsw_pwr->i915_request)
  4265. __intel_set_power_well(hsw_pwr->device, true);
  4266. spin_unlock_irq(&hsw_pwr->lock);
  4267. }
  4268. EXPORT_SYMBOL_GPL(i915_request_power_well);
  4269. /* Display audio driver power well release */
  4270. void i915_release_power_well(void)
  4271. {
  4272. if (WARN_ON(!hsw_pwr))
  4273. return;
  4274. spin_lock_irq(&hsw_pwr->lock);
  4275. WARN_ON(!hsw_pwr->count);
  4276. if (!--hsw_pwr->count &&
  4277. !hsw_pwr->i915_request)
  4278. __intel_set_power_well(hsw_pwr->device, false);
  4279. spin_unlock_irq(&hsw_pwr->lock);
  4280. }
  4281. EXPORT_SYMBOL_GPL(i915_release_power_well);
  4282. int i915_init_power_well(struct drm_device *dev)
  4283. {
  4284. struct drm_i915_private *dev_priv = dev->dev_private;
  4285. hsw_pwr = &dev_priv->power_well;
  4286. hsw_pwr->device = dev;
  4287. spin_lock_init(&hsw_pwr->lock);
  4288. hsw_pwr->count = 0;
  4289. return 0;
  4290. }
  4291. void i915_remove_power_well(struct drm_device *dev)
  4292. {
  4293. hsw_pwr = NULL;
  4294. }
  4295. void intel_set_power_well(struct drm_device *dev, bool enable)
  4296. {
  4297. struct drm_i915_private *dev_priv = dev->dev_private;
  4298. struct i915_power_well *power_well = &dev_priv->power_well;
  4299. if (!HAS_POWER_WELL(dev))
  4300. return;
  4301. if (!i915_disable_power_well && !enable)
  4302. return;
  4303. spin_lock_irq(&power_well->lock);
  4304. power_well->i915_request = enable;
  4305. /* only reject "disable" power well request */
  4306. if (power_well->count && !enable) {
  4307. spin_unlock_irq(&power_well->lock);
  4308. return;
  4309. }
  4310. __intel_set_power_well(dev, enable);
  4311. spin_unlock_irq(&power_well->lock);
  4312. }
  4313. /*
  4314. * Starting with Haswell, we have a "Power Down Well" that can be turned off
  4315. * when not needed anymore. We have 4 registers that can request the power well
  4316. * to be enabled, and it will only be disabled if none of the registers is
  4317. * requesting it to be enabled.
  4318. */
  4319. void intel_init_power_well(struct drm_device *dev)
  4320. {
  4321. struct drm_i915_private *dev_priv = dev->dev_private;
  4322. if (!HAS_POWER_WELL(dev))
  4323. return;
  4324. /* For now, we need the power well to be always enabled. */
  4325. intel_set_power_well(dev, true);
  4326. /* We're taking over the BIOS, so clear any requests made by it since
  4327. * the driver is in charge now. */
  4328. if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
  4329. I915_WRITE(HSW_PWR_WELL_BIOS, 0);
  4330. }
  4331. /* Set up chip specific power management-related functions */
  4332. void intel_init_pm(struct drm_device *dev)
  4333. {
  4334. struct drm_i915_private *dev_priv = dev->dev_private;
  4335. if (I915_HAS_FBC(dev)) {
  4336. if (HAS_PCH_SPLIT(dev)) {
  4337. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  4338. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  4339. dev_priv->display.enable_fbc =
  4340. gen7_enable_fbc;
  4341. else
  4342. dev_priv->display.enable_fbc =
  4343. ironlake_enable_fbc;
  4344. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  4345. } else if (IS_GM45(dev)) {
  4346. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  4347. dev_priv->display.enable_fbc = g4x_enable_fbc;
  4348. dev_priv->display.disable_fbc = g4x_disable_fbc;
  4349. } else if (IS_CRESTLINE(dev)) {
  4350. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  4351. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  4352. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  4353. }
  4354. /* 855GM needs testing */
  4355. }
  4356. /* For cxsr */
  4357. if (IS_PINEVIEW(dev))
  4358. i915_pineview_get_mem_freq(dev);
  4359. else if (IS_GEN5(dev))
  4360. i915_ironlake_get_mem_freq(dev);
  4361. /* For FIFO watermark updates */
  4362. if (HAS_PCH_SPLIT(dev)) {
  4363. if (IS_GEN5(dev)) {
  4364. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  4365. dev_priv->display.update_wm = ironlake_update_wm;
  4366. else {
  4367. DRM_DEBUG_KMS("Failed to get proper latency. "
  4368. "Disable CxSR\n");
  4369. dev_priv->display.update_wm = NULL;
  4370. }
  4371. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  4372. } else if (IS_GEN6(dev)) {
  4373. if (SNB_READ_WM0_LATENCY()) {
  4374. dev_priv->display.update_wm = sandybridge_update_wm;
  4375. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  4376. } else {
  4377. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4378. "Disable CxSR\n");
  4379. dev_priv->display.update_wm = NULL;
  4380. }
  4381. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  4382. } else if (IS_IVYBRIDGE(dev)) {
  4383. if (SNB_READ_WM0_LATENCY()) {
  4384. dev_priv->display.update_wm = ivybridge_update_wm;
  4385. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  4386. } else {
  4387. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4388. "Disable CxSR\n");
  4389. dev_priv->display.update_wm = NULL;
  4390. }
  4391. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  4392. } else if (IS_HASWELL(dev)) {
  4393. if (I915_READ64(MCH_SSKPD)) {
  4394. dev_priv->display.update_wm = haswell_update_wm;
  4395. dev_priv->display.update_sprite_wm =
  4396. haswell_update_sprite_wm;
  4397. } else {
  4398. DRM_DEBUG_KMS("Failed to read display plane latency. "
  4399. "Disable CxSR\n");
  4400. dev_priv->display.update_wm = NULL;
  4401. }
  4402. dev_priv->display.init_clock_gating = haswell_init_clock_gating;
  4403. } else
  4404. dev_priv->display.update_wm = NULL;
  4405. } else if (IS_VALLEYVIEW(dev)) {
  4406. dev_priv->display.update_wm = valleyview_update_wm;
  4407. dev_priv->display.init_clock_gating =
  4408. valleyview_init_clock_gating;
  4409. } else if (IS_PINEVIEW(dev)) {
  4410. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  4411. dev_priv->is_ddr3,
  4412. dev_priv->fsb_freq,
  4413. dev_priv->mem_freq)) {
  4414. DRM_INFO("failed to find known CxSR latency "
  4415. "(found ddr%s fsb freq %d, mem freq %d), "
  4416. "disabling CxSR\n",
  4417. (dev_priv->is_ddr3 == 1) ? "3" : "2",
  4418. dev_priv->fsb_freq, dev_priv->mem_freq);
  4419. /* Disable CxSR and never update its watermark again */
  4420. pineview_disable_cxsr(dev);
  4421. dev_priv->display.update_wm = NULL;
  4422. } else
  4423. dev_priv->display.update_wm = pineview_update_wm;
  4424. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  4425. } else if (IS_G4X(dev)) {
  4426. dev_priv->display.update_wm = g4x_update_wm;
  4427. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  4428. } else if (IS_GEN4(dev)) {
  4429. dev_priv->display.update_wm = i965_update_wm;
  4430. if (IS_CRESTLINE(dev))
  4431. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  4432. else if (IS_BROADWATER(dev))
  4433. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  4434. } else if (IS_GEN3(dev)) {
  4435. dev_priv->display.update_wm = i9xx_update_wm;
  4436. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  4437. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  4438. } else if (IS_I865G(dev)) {
  4439. dev_priv->display.update_wm = i830_update_wm;
  4440. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  4441. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4442. } else if (IS_I85X(dev)) {
  4443. dev_priv->display.update_wm = i9xx_update_wm;
  4444. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  4445. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  4446. } else {
  4447. dev_priv->display.update_wm = i830_update_wm;
  4448. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  4449. if (IS_845G(dev))
  4450. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  4451. else
  4452. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4453. }
  4454. }
  4455. static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
  4456. {
  4457. u32 gt_thread_status_mask;
  4458. if (IS_HASWELL(dev_priv->dev))
  4459. gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
  4460. else
  4461. gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
  4462. /* w/a for a sporadic read returning 0 by waiting for the GT
  4463. * thread to wake up.
  4464. */
  4465. if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
  4466. DRM_ERROR("GT thread status wait timed out\n");
  4467. }
  4468. static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
  4469. {
  4470. I915_WRITE_NOTRACE(FORCEWAKE, 0);
  4471. POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
  4472. }
  4473. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  4474. {
  4475. if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
  4476. FORCEWAKE_ACK_TIMEOUT_MS))
  4477. DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4478. I915_WRITE_NOTRACE(FORCEWAKE, 1);
  4479. POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
  4480. if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
  4481. FORCEWAKE_ACK_TIMEOUT_MS))
  4482. DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  4483. /* WaRsForcewakeWaitTC0:snb */
  4484. __gen6_gt_wait_for_thread_c0(dev_priv);
  4485. }
  4486. static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
  4487. {
  4488. I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
  4489. /* something from same cacheline, but !FORCEWAKE_MT */
  4490. POSTING_READ(ECOBUS);
  4491. }
  4492. static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
  4493. {
  4494. u32 forcewake_ack;
  4495. if (IS_HASWELL(dev_priv->dev))
  4496. forcewake_ack = FORCEWAKE_ACK_HSW;
  4497. else
  4498. forcewake_ack = FORCEWAKE_MT_ACK;
  4499. if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
  4500. FORCEWAKE_ACK_TIMEOUT_MS))
  4501. DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4502. I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
  4503. /* something from same cacheline, but !FORCEWAKE_MT */
  4504. POSTING_READ(ECOBUS);
  4505. if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
  4506. FORCEWAKE_ACK_TIMEOUT_MS))
  4507. DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
  4508. /* WaRsForcewakeWaitTC0:ivb,hsw */
  4509. __gen6_gt_wait_for_thread_c0(dev_priv);
  4510. }
  4511. /*
  4512. * Generally this is called implicitly by the register read function. However,
  4513. * if some sequence requires the GT to not power down then this function should
  4514. * be called at the beginning of the sequence followed by a call to
  4515. * gen6_gt_force_wake_put() at the end of the sequence.
  4516. */
  4517. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  4518. {
  4519. unsigned long irqflags;
  4520. spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  4521. if (dev_priv->forcewake_count++ == 0)
  4522. dev_priv->gt.force_wake_get(dev_priv);
  4523. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  4524. }
  4525. void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
  4526. {
  4527. u32 gtfifodbg;
  4528. gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
  4529. if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
  4530. "MMIO read or write has been dropped %x\n", gtfifodbg))
  4531. I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
  4532. }
  4533. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  4534. {
  4535. I915_WRITE_NOTRACE(FORCEWAKE, 0);
  4536. /* something from same cacheline, but !FORCEWAKE */
  4537. POSTING_READ(ECOBUS);
  4538. gen6_gt_check_fifodbg(dev_priv);
  4539. }
  4540. static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
  4541. {
  4542. I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
  4543. /* something from same cacheline, but !FORCEWAKE_MT */
  4544. POSTING_READ(ECOBUS);
  4545. gen6_gt_check_fifodbg(dev_priv);
  4546. }
  4547. /*
  4548. * see gen6_gt_force_wake_get()
  4549. */
  4550. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  4551. {
  4552. unsigned long irqflags;
  4553. spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  4554. if (--dev_priv->forcewake_count == 0)
  4555. dev_priv->gt.force_wake_put(dev_priv);
  4556. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  4557. }
  4558. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  4559. {
  4560. int ret = 0;
  4561. if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
  4562. int loop = 500;
  4563. u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  4564. while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  4565. udelay(10);
  4566. fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  4567. }
  4568. if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
  4569. ++ret;
  4570. dev_priv->gt_fifo_count = fifo;
  4571. }
  4572. dev_priv->gt_fifo_count--;
  4573. return ret;
  4574. }
  4575. static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
  4576. {
  4577. I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
  4578. /* something from same cacheline, but !FORCEWAKE_VLV */
  4579. POSTING_READ(FORCEWAKE_ACK_VLV);
  4580. }
  4581. static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
  4582. {
  4583. if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
  4584. FORCEWAKE_ACK_TIMEOUT_MS))
  4585. DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
  4586. I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
  4587. I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
  4588. _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
  4589. if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
  4590. FORCEWAKE_ACK_TIMEOUT_MS))
  4591. DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
  4592. if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
  4593. FORCEWAKE_KERNEL),
  4594. FORCEWAKE_ACK_TIMEOUT_MS))
  4595. DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
  4596. /* WaRsForcewakeWaitTC0:vlv */
  4597. __gen6_gt_wait_for_thread_c0(dev_priv);
  4598. }
  4599. static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
  4600. {
  4601. I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
  4602. I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
  4603. _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
  4604. /* The below doubles as a POSTING_READ */
  4605. gen6_gt_check_fifodbg(dev_priv);
  4606. }
  4607. void intel_gt_reset(struct drm_device *dev)
  4608. {
  4609. struct drm_i915_private *dev_priv = dev->dev_private;
  4610. if (IS_VALLEYVIEW(dev)) {
  4611. vlv_force_wake_reset(dev_priv);
  4612. } else if (INTEL_INFO(dev)->gen >= 6) {
  4613. __gen6_gt_force_wake_reset(dev_priv);
  4614. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  4615. __gen6_gt_force_wake_mt_reset(dev_priv);
  4616. }
  4617. }
  4618. void intel_gt_init(struct drm_device *dev)
  4619. {
  4620. struct drm_i915_private *dev_priv = dev->dev_private;
  4621. spin_lock_init(&dev_priv->gt_lock);
  4622. intel_gt_reset(dev);
  4623. if (IS_VALLEYVIEW(dev)) {
  4624. dev_priv->gt.force_wake_get = vlv_force_wake_get;
  4625. dev_priv->gt.force_wake_put = vlv_force_wake_put;
  4626. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  4627. dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
  4628. dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
  4629. } else if (IS_GEN6(dev)) {
  4630. dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
  4631. dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
  4632. }
  4633. INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
  4634. intel_gen6_powersave_work);
  4635. }
  4636. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
  4637. {
  4638. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  4639. if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
  4640. DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
  4641. return -EAGAIN;
  4642. }
  4643. I915_WRITE(GEN6_PCODE_DATA, *val);
  4644. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
  4645. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  4646. 500)) {
  4647. DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
  4648. return -ETIMEDOUT;
  4649. }
  4650. *val = I915_READ(GEN6_PCODE_DATA);
  4651. I915_WRITE(GEN6_PCODE_DATA, 0);
  4652. return 0;
  4653. }
  4654. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
  4655. {
  4656. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  4657. if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
  4658. DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
  4659. return -EAGAIN;
  4660. }
  4661. I915_WRITE(GEN6_PCODE_DATA, val);
  4662. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
  4663. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  4664. 500)) {
  4665. DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
  4666. return -ETIMEDOUT;
  4667. }
  4668. I915_WRITE(GEN6_PCODE_DATA, 0);
  4669. return 0;
  4670. }
  4671. int vlv_gpu_freq(int ddr_freq, int val)
  4672. {
  4673. int mult, base;
  4674. switch (ddr_freq) {
  4675. case 800:
  4676. mult = 20;
  4677. base = 120;
  4678. break;
  4679. case 1066:
  4680. mult = 22;
  4681. base = 133;
  4682. break;
  4683. case 1333:
  4684. mult = 21;
  4685. base = 125;
  4686. break;
  4687. default:
  4688. return -1;
  4689. }
  4690. return ((val - 0xbd) * mult) + base;
  4691. }
  4692. int vlv_freq_opcode(int ddr_freq, int val)
  4693. {
  4694. int mult, base;
  4695. switch (ddr_freq) {
  4696. case 800:
  4697. mult = 20;
  4698. base = 120;
  4699. break;
  4700. case 1066:
  4701. mult = 22;
  4702. base = 133;
  4703. break;
  4704. case 1333:
  4705. mult = 21;
  4706. base = 125;
  4707. break;
  4708. default:
  4709. return -1;
  4710. }
  4711. val /= mult;
  4712. val -= base / mult;
  4713. val += 0xbd;
  4714. if (val > 0xea)
  4715. val = 0xea;
  4716. return val;
  4717. }