 Sergei Shtylyov
|
9370b35175
[MIPS] Save write-only Config.OD from being clobbered
|
19 years ago |
 Kumba
|
44d921b246
[MIPS] Treat R14000 like R10000.
|
19 years ago |
 Ralf Baechle
|
7f3f1d01a9
[MIPS] Fix deadlock on MP with cache aliases.
|
19 years ago |
 Nigel Stephens
|
98a41de99a
[MIPS] Add missing 34K processor IDs
|
19 years ago |
 Atsushi Nemoto
|
3c68da798a
[MIPS] Use __ffs() instead of ffs() for waybit calculation.
|
19 years ago |
|
Ralf Baechle
|
7e3bfc7cfc
[MIPS] Handle IDE PIO cache aliases on SMP.
|
19 years ago |
|
Atsushi Nemoto
|
67a3f6de93
[MIPS] Fix tx49_blast_icache32_page_indexed.
|
19 years ago |
|
Atsushi Nemoto
|
de862b488e
[MIPS] TX49XX has prefetch.
|
19 years ago |
|
Atsushi Nemoto
|
de62893bc0
[MIPS] local_r4k_flush_cache_page fix
|
19 years ago |
|
Ralf Baechle
|
4debe4f963
[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
|
19 years ago |
|
Atsushi Nemoto
|
41700e7399
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
|
19 years ago |
|
Atsushi Nemoto
|
d4264f1839
[MIPS] Remove wrong __user tags.
|
19 years ago |
|
Ralf Baechle
|
e7958bb90d
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
|
19 years ago |
|
Ralf Baechle
|
6ec25809c1
Rename page argument of flush_cache_page to something more descriptive.
|
20 years ago |
|
Ralf Baechle
|
02cf211968
Cleanup the mess in cpu_cache_init.
|
20 years ago |
 Thiemo Seufer
|
10a3dabddd
Add/Fix missing bit of R4600 hit cacheop workaround.
|
20 years ago |
|
Thiemo Seufer
|
02fe2c9ce3
Minor code cleanup.
|
20 years ago |
|
Thiemo Seufer
|
d8748a3abf
More .set push/pop.
|
20 years ago |
|
Thiemo Seufer
|
330cfe016b
Let r4600 PRID detection match only legacy CPUs, cleanups.
|
20 years ago |
|
Ralf Baechle
|
1d40cfcd34
Avoid SMP cacheflushes. This is a minor optimization of startup but
|
20 years ago |
|
Ralf Baechle
|
e01402b115
More AP / SP bits for the 34K, the Malta bits and things. Still wants
|
20 years ago |
|
Ralf Baechle
|
ec74e361f1
Mark a few variables __read_mostly.
|
20 years ago |
|
Ralf Baechle
|
cc61c1fede
MIPS R2 instruction hazard handling.
|
20 years ago |
|
Thiemo Seufer
|
ba5187dbb4
Better interface to run uncached cache setup code.
|
20 years ago |
|
Ralf Baechle
|
fe00f943e0
Sparseify MIPS.
|
20 years ago |
 Pete Popov
|
e3ad1c23ba
Base Au1200 2.6 support.
|
20 years ago |
|
Thiemo Seufer
|
26a51b270f
Use intermediate variable.
|
20 years ago |
|
Ralf Baechle
|
79acf83e50
Moves a test which determines if we actually need to perform a
|
20 years ago |
|
Ralf Baechle
|
c6e8b58771
Update MIPS to use the 4-level pagetable code thereby getting rid of
|
20 years ago |
|
Ralf Baechle
|
505403b6a0
25Kf is also physically indexed.
|
20 years ago |
