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@@ -25,7 +25,10 @@
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#include <asm/cpu.h>
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#include <asm/war.h>
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-#define half_scache_line_size() (cpu_scache_line_size() >> 1)
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+#define half_scache_line_size() (cpu_scache_line_size() >> 1)
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+#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
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+#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
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+
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/*
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* Maximum sizes:
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@@ -198,14 +201,14 @@ static inline void build_cdex_p(void)
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if (store_offset & (cpu_dcache_line_size() - 1))
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return;
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- if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) {
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+ if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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build_nop();
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build_nop();
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build_nop();
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build_nop();
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}
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- if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
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+ if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x8c200000); /* lw $zero, ($at) */
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mi.c_format.opcode = cache_op;
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@@ -361,7 +364,7 @@ void __init build_clear_page(void)
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build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0));
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- if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
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+ if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
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dest = label();
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@@ -417,7 +420,7 @@ void __init build_copy_page(void)
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build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0));
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- if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
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+ if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
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dest = label();
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