 Jörn Engel
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6ab3d5624e
Remove obsolete #include <linux/config.h>
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19 years ago |
 Ralf Baechle
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2e78ae3f48
[MIPS] 74K: Assume it will also have an AR bit in config7
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19 years ago |
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Ralf Baechle
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beab375a48
[MIPS] Treat CPUs with AR bit as physically indexed.
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19 years ago |
 Chris Dearman
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73f403527b
[MIPS] Fix handling of 0 length I & D caches.
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19 years ago |
|
Chris Dearman
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9318c51acd
[MIPS] MIPS32/MIPS64 secondary cache management
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19 years ago |
 Sergei Shtylyov
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9370b35175
[MIPS] Save write-only Config.OD from being clobbered
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19 years ago |
 Kumba
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44d921b246
[MIPS] Treat R14000 like R10000.
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19 years ago |
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Ralf Baechle
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7f3f1d01a9
[MIPS] Fix deadlock on MP with cache aliases.
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19 years ago |
 Nigel Stephens
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98a41de99a
[MIPS] Add missing 34K processor IDs
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19 years ago |
 Atsushi Nemoto
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3c68da798a
[MIPS] Use __ffs() instead of ffs() for waybit calculation.
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19 years ago |
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Ralf Baechle
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7e3bfc7cfc
[MIPS] Handle IDE PIO cache aliases on SMP.
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19 years ago |
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Atsushi Nemoto
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67a3f6de93
[MIPS] Fix tx49_blast_icache32_page_indexed.
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19 years ago |
|
Atsushi Nemoto
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de862b488e
[MIPS] TX49XX has prefetch.
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19 years ago |
|
Atsushi Nemoto
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de62893bc0
[MIPS] local_r4k_flush_cache_page fix
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19 years ago |
|
Ralf Baechle
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4debe4f963
[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
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19 years ago |
|
Atsushi Nemoto
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41700e7399
[MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
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19 years ago |
|
Atsushi Nemoto
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d4264f1839
[MIPS] Remove wrong __user tags.
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19 years ago |
|
Ralf Baechle
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e7958bb90d
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
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19 years ago |
|
Ralf Baechle
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6ec25809c1
Rename page argument of flush_cache_page to something more descriptive.
|
20 years ago |
|
Ralf Baechle
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02cf211968
Cleanup the mess in cpu_cache_init.
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20 years ago |
 Thiemo Seufer
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10a3dabddd
Add/Fix missing bit of R4600 hit cacheop workaround.
|
20 years ago |
|
Thiemo Seufer
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02fe2c9ce3
Minor code cleanup.
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20 years ago |
|
Thiemo Seufer
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d8748a3abf
More .set push/pop.
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20 years ago |
|
Thiemo Seufer
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330cfe016b
Let r4600 PRID detection match only legacy CPUs, cleanups.
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20 years ago |
|
Ralf Baechle
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1d40cfcd34
Avoid SMP cacheflushes. This is a minor optimization of startup but
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20 years ago |
|
Ralf Baechle
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e01402b115
More AP / SP bits for the 34K, the Malta bits and things. Still wants
|
20 years ago |
|
Ralf Baechle
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ec74e361f1
Mark a few variables __read_mostly.
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20 years ago |
|
Ralf Baechle
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cc61c1fede
MIPS R2 instruction hazard handling.
|
20 years ago |
|
Thiemo Seufer
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ba5187dbb4
Better interface to run uncached cache setup code.
|
20 years ago |
|
Ralf Baechle
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fe00f943e0
Sparseify MIPS.
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20 years ago |
