 Linus Torvalds
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5a5a1bf099
Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
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%!s(int64=12) %!d(string=hai) anos |
 Aravind Gopalakrishnan
|
94c1acf2c8
amd64_edac: Add Family 16h support
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%!s(int64=12) %!d(string=hai) anos |
 Jan Beulich
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c391c78846
x86: Constify a few items
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%!s(int64=12) %!d(string=hai) anos |
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Linus Torvalds
|
5b160bd426
Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
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%!s(int64=13) %!d(string=hai) anos |
 Borislav Petkov
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24214449b0
x86, amd_nb: Export model 0x10 and later PCI id
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%!s(int64=13) %!d(string=hai) anos |
 Joe Perches
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c767a54ba0
x86/debug: Add KERN_<LEVEL> to bare printks, convert printks to pr_<level>
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%!s(int64=13) %!d(string=hai) anos |
|
Linus Torvalds
|
7b67e75147
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci
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%!s(int64=13) %!d(string=hai) anos |
 Bjorn Helgaas
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24d25dbfa6
x86/PCI: amd: factor out MMCONFIG discovery
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%!s(int64=13) %!d(string=hai) anos |
 Kevin Winchester
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141168c36c
x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86'
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%!s(int64=13) %!d(string=hai) anos |
 Borislav Petkov
|
cb6c8520f6
x86, amd-nb: Rename CPU PCI id define for F4
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%!s(int64=14) %!d(string=hai) anos |
|
Linus Torvalds
|
978ca164bd
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
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%!s(int64=14) %!d(string=hai) anos |
|
Borislav Petkov
|
cb293250c7
PCI: Rename CPU PCI id define
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%!s(int64=14) %!d(string=hai) anos |
|
Borislav Petkov
|
84fd1d35cc
x86, amd-nb: Misc cleanliness fixes
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%!s(int64=14) %!d(string=hai) anos |
 Jan Beulich
|
691269f0d9
x86: Adjust section placement in AMD northbridge related code
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%!s(int64=14) %!d(string=hai) anos |
 Hans Rosenfeld
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cabb5bd7ff
x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs
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%!s(int64=14) %!d(string=hai) anos |
|
Hans Rosenfeld
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41b2610c34
x86, amd: Extend AMD northbridge caching code to support "Link Control" devices
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%!s(int64=14) %!d(string=hai) anos |
|
Hans Rosenfeld
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b453de02b7
x86, amd: Enable L3 cache index disable on family 0x15
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%!s(int64=14) %!d(string=hai) anos |
|
Jan Beulich
|
24d9b70b8c
x86: Use PCI method for enabling AMD extended config space before MSR method
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%!s(int64=14) %!d(string=hai) anos |
|
Hans Rosenfeld
|
f658bcfb26
x86, cacheinfo: Cleanup L3 cache index disable support
|
%!s(int64=14) %!d(string=hai) anos |
|
Hans Rosenfeld
|
9653a5c76c
x86, amd-nb: Cleanup AMD northbridge caching code
|
%!s(int64=14) %!d(string=hai) anos |
|
Hans Rosenfeld
|
eec1d4fa00
x86, amd-nb: Complete the rename of AMD NB and related code
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%!s(int64=14) %!d(string=hai) anos |
 Andreas Herrmann
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5c80cc78de
x86, amd_nb: Enable GART support for AMD family 0x15 CPUs
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%!s(int64=14) %!d(string=hai) anos |
|
Andreas Herrmann
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23ac4ae827
x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB
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%!s(int64=15) %!d(string=hai) anos |
