 Rob Herring
|
6e7aceeb7c
ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init
|
12 years ago |
 Gregory CLEMENT
|
8a3a180d21
ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
|
12 years ago |
|
Gregory CLEMENT
|
8b827c60a1
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
|
12 years ago |
|
Rob Herring
|
74ddcdb868
ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
|
12 years ago |
|
Gregory CLEMENT
|
b8db6b886a
ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl
|
12 years ago |
|
Gregory CLEMENT
|
6248d0602f
ARM: 7545/1: cache-l2x0: make outer_cache_fns a field of l2x0_of_data
|
12 years ago |
 Linus Torvalds
|
0e51793e16
Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm
|
12 years ago |
 Yilu Mao
|
9d4876f039
ARM: 7507/1: cache-l2x0.c: save the final aux ctrl value for resuming
|
13 years ago |
 Uwe Kleine-König
|
e5b5d0209f
ARM: cache-l2x0: add a const qualifier
|
13 years ago |
 Will Deacon
|
ab4d536890
ARM: 7398/1: l2x0: only write to debug registers on PL310
|
13 years ago |
|
Will Deacon
|
f154fe9b80
ARM: 7397/1: l2x0: only apply workaround for erratum #753970 on PL310
|
13 years ago |
 Russell King
|
3e175ca4ca
ARM: cache-l2x0.c: consistently use u32
|
13 years ago |
|
Will Deacon
|
fa0ce4035d
ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
|
13 years ago |
|
Linus Torvalds
|
3cfef95246
Merge branch 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
|
13 years ago |
 Barry Song
|
91c2ebb90b
ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode
|
13 years ago |
 Barry Song
|
74d41f39a9
ARM: 7090/1: CACHE-L2X0: filter start address can be 0 and is often 0
|
13 years ago |
|
Barry Song
|
1caf30924f
ARM: 7089/1: L2X0: add explicit cpu_relax() for busy wait loop
|
14 years ago |
|
Rob Herring
|
8c369264b6
ARM: 7009/1: l2x0: Add OF based initialization
|
14 years ago |
 Thomas Gleixner
|
bd31b85960
locking, ARM: Annotate low level hw locks as raw
|
16 years ago |
 Linus Walleij
|
bac7e6ecf6
ARM: 7080/1: l2x0: make sure I&D are not locked down on init
|
14 years ago |
|
Will Deacon
|
38a8914f9a
ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
|
14 years ago |
|
Russell King
|
1f0090a1ea
Merge branch 'misc' into devel
|
14 years ago |
 Santosh Shilimkar
|
2839e06c95
ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
|
14 years ago |
 Srinidhi Kasagar
|
885028e4ba
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
|
14 years ago |
|
Santosh Shilimkar
|
444457c1f5
ARM: l2x0: Optimise the range based operations
|
15 years ago |
|
Santosh Shilimkar
|
5ba7037228
ARM: l2x0: Determine the cache size
|
15 years ago |
 Thomas Gleixner
|
2fd8658931
arm: Implement l2x0 cache disable functions
|
15 years ago |
 Catalin Marinas
|
9a6655e49f
ARM: Improve the L2 cache performance when PL310 is used
|
15 years ago |
|
Catalin Marinas
|
6775a558fe
ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
|
15 years ago |
 Sascha Hauer
|
4082cfa776
ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
|
15 years ago |
