Commit History

Autor SHA1 Mensaxe Data
  Ben Skeggs ec23802d61 drm/nv50: drop explicit yields in favour of smaller PFIFO timeslice %!s(int64=14) %!d(string=hai) anos
  Ben Skeggs a11c3198c9 drm/nv50: import new vm code %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs d908175cca drm/nouveau: make fifo.create_context() responsible for mapping control regs %!s(int64=14) %!d(string=hai) anos
  Ben Skeggs 5178d40dff drm/nouveau: move PFIFO ISR into nv04_fifo.c %!s(int64=14) %!d(string=hai) anos
  Francisco Jerez 3945e47543 drm/nouveau: Refactor context destruction to avoid a lock ordering issue. %!s(int64=14) %!d(string=hai) anos
  Ben Skeggs cff5c13324 drm/nouveau: add more fine-grained locking to channel list + structures %!s(int64=14) %!d(string=hai) anos
  Ben Skeggs 56ac747535 drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hang %!s(int64=14) %!d(string=hai) anos
  Ben Skeggs e05c5a317e drm/nouveau: tidy ram{ht,fc,ro} a bit %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs a8eaebc6c5 drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanity %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs de3a6c0a3b drm/nouveau: rebase per-channel pramin heap offsets to 0 %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs b3beb167af drm/nouveau: modify object accessors, offset in bytes rather than dwords %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs ca6adb8a21 drm/nv50: fix RAMHT size %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs ac94a343c7 drm/nv50: cleanup nv50_fifo.c %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs f56cb86f9a drm/nouveau: add instmem flush() hook %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs 9a391ad8a2 drm/nv50: switch to indirect push buffer controls %!s(int64=15) %!d(string=hai) anos
  Maarten Maathuis ff9e5279b1 drm/nouveau: protect channel create/destroy and irq handler with a spinlock %!s(int64=15) %!d(string=hai) anos
  Maarten Maathuis a87ff62a80 drm/nv50: delete ramfc object after disabling fifo, not before %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs 134f248bea drm/nv50: fix alignment of per-channel fifo cache %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs 7fb8ec8e2b drm/nv50: restore correct cache1 get/put address on fifoctx load %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs 3c8868d3db drm/nv50: fix two potential suspend/resume oopses %!s(int64=15) %!d(string=hai) anos
  Ben Skeggs 6ee738610f drm/nouveau: Add DRM driver for NVIDIA GPUs %!s(int64=15) %!d(string=hai) anos