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@@ -101,8 +101,8 @@ retry:
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if (l == (1L << limit)) {
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if (limit < 4) {
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limit++;
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- reg = DART_IN(DART_CNTL);
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- reg &= ~inv_bit;
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+ reg = DART_IN(DART_CNTL);
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+ reg &= ~inv_bit;
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DART_OUT(DART_CNTL, reg);
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goto retry;
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} else
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@@ -111,11 +111,39 @@ retry:
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}
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}
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+static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
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+{
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+ unsigned int reg;
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+ unsigned int l, limit;
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+
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+ reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
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+ (bus_rpn & DART_CNTL_U4_IONE_MASK);
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+ DART_OUT(DART_CNTL, reg);
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+
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+ limit = 0;
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+wait_more:
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+ l = 0;
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+ while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
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+ rmb();
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+ l++;
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+ }
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+
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+ if (l == (1L << limit)) {
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+ if (limit < 4) {
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+ limit++;
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+ goto wait_more;
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+ } else
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+ panic("DART: TLB did not flush after waiting a long "
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+ "time. Buggy U4 ?");
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+ }
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+}
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+
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static void dart_flush(struct iommu_table *tbl)
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{
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- if (dart_dirty)
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+ if (dart_dirty) {
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dart_tlb_invalidate_all();
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- dart_dirty = 0;
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+ dart_dirty = 0;
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+ }
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}
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static void dart_build(struct iommu_table *tbl, long index,
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@@ -124,6 +152,7 @@ static void dart_build(struct iommu_table *tbl, long index,
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{
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unsigned int *dp;
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unsigned int rpn;
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+ long l;
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DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
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@@ -135,7 +164,8 @@ static void dart_build(struct iommu_table *tbl, long index,
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/* On U3, all memory is contigous, so we can move this
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* out of the loop.
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*/
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- while (npages--) {
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+ l = npages;
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+ while (l--) {
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rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
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*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
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@@ -143,7 +173,14 @@ static void dart_build(struct iommu_table *tbl, long index,
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uaddr += DART_PAGE_SIZE;
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}
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- dart_dirty = 1;
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+ if (dart_is_u4) {
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+ rpn = index;
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+ mb(); /* make sure all updates have reached memory */
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+ while (npages--)
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+ dart_tlb_invalidate_one(rpn++);
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+ } else {
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+ dart_dirty = 1;
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+ }
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}
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