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@@ -4257,51 +4257,6 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
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}
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}
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-static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
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- struct drm_display_mode *adjusted_mode)
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-{
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- struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- int pipe = intel_crtc->pipe;
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- u32 temp;
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-
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- temp = I915_READ(LVDS);
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- temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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- if (pipe == 1) {
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- temp |= LVDS_PIPEB_SELECT;
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- } else {
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- temp &= ~LVDS_PIPEB_SELECT;
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- }
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- /* set the corresponsding LVDS_BORDER bit */
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- temp |= dev_priv->lvds_border_bits;
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- /* Set the B0-B3 data pairs corresponding to whether we're going to
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- * set the DPLLs for dual-channel mode or not.
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- */
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- if (clock->p2 == 7)
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- temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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- else
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- temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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-
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- /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
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- * appropriately here, but we need to look more thoroughly into how
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- * panels behave in the two modes.
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- */
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- /* set the dithering flag on LVDS as needed */
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- if (INTEL_INFO(dev)->gen >= 4) {
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- if (dev_priv->lvds_dither)
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- temp |= LVDS_ENABLE_DITHER;
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- else
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- temp &= ~LVDS_ENABLE_DITHER;
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- }
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- temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
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- if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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- temp |= LVDS_HSYNC_POLARITY;
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- if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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- temp |= LVDS_VSYNC_POLARITY;
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- I915_WRITE(LVDS, temp);
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-}
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-
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static void vlv_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@@ -4484,13 +4439,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
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- * This is an exception to the general rule that mode_set doesn't turn
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- * things on.
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- */
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- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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- intel_update_lvds(crtc, clock, adjusted_mode);
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-
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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intel_dp_set_m_n(crtc, mode, adjusted_mode);
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@@ -4566,13 +4514,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
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- * This is an exception to the general rule that mode_set doesn't turn
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- * things on.
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- */
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- if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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- intel_update_lvds(crtc, clock, adjusted_mode);
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-
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I915_WRITE(DPLL(pipe), dpll);
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/* Wait for the clocks to stabilize. */
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