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@@ -45,7 +45,6 @@
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#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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-static void intel_update_watermarks(struct drm_device *dev);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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@@ -4820,7 +4819,7 @@ static void ironlake_update_wm(struct drm_device *dev)
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*/
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}
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-void sandybridge_update_wm(struct drm_device *dev)
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+static void sandybridge_update_wm(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
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@@ -5125,7 +5124,7 @@ static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
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* We don't use the sprite, so we can ignore that. And on Crestline we have
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* to set the non-SR watermarks to 8.
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*/
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-static void intel_update_watermarks(struct drm_device *dev)
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+void intel_update_watermarks(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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