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@@ -59,6 +59,24 @@ struct spi_imx_config {
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int cs;
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int cs;
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};
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};
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+enum spi_imx_devtype {
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+ SPI_IMX_VER_IMX1,
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+ SPI_IMX_VER_0_0,
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+ SPI_IMX_VER_0_4,
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+ SPI_IMX_VER_0_5,
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+ SPI_IMX_VER_0_7,
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+ SPI_IMX_VER_AUTODETECT,
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+};
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+
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+struct spi_imx_data;
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+
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+struct spi_imx_devtype_data {
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+ void (*intctrl)(struct spi_imx_data *, int);
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+ int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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+ void (*trigger)(struct spi_imx_data *);
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+ int (*rx_available)(struct spi_imx_data *);
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+};
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+
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struct spi_imx_data {
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struct spi_imx_data {
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struct spi_bitbang bitbang;
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struct spi_bitbang bitbang;
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@@ -76,11 +94,7 @@ struct spi_imx_data {
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const void *tx_buf;
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const void *tx_buf;
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unsigned int txfifo; /* number of words pushed in tx FIFO */
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unsigned int txfifo; /* number of words pushed in tx FIFO */
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- /* SoC specific functions */
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- void (*intctrl)(struct spi_imx_data *, int);
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- int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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- void (*trigger)(struct spi_imx_data *);
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- int (*rx_available)(struct spi_imx_data *);
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+ struct spi_imx_devtype_data devtype_data;
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};
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};
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#define MXC_SPI_BUF_RX(type) \
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#define MXC_SPI_BUF_RX(type) \
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@@ -178,7 +192,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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* the i.MX35 has a slightly different register layout for bits
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* the i.MX35 has a slightly different register layout for bits
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* we do not use here.
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* we do not use here.
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*/
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*/
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-static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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+static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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{
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unsigned int val = 0;
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unsigned int val = 0;
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@@ -190,7 +204,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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writel(val, spi_imx->base + MXC_CSPIINT);
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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}
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-static void mx31_trigger(struct spi_imx_data *spi_imx)
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+static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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{
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{
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unsigned int reg;
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unsigned int reg;
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@@ -199,7 +213,7 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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}
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-static int mx31_config(struct spi_imx_data *spi_imx,
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+static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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struct spi_imx_config *config)
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{
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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@@ -232,7 +246,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
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return 0;
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return 0;
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}
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}
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-static int mx31_rx_available(struct spi_imx_data *spi_imx)
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+static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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{
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{
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}
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}
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@@ -250,7 +264,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
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#define MX27_CSPICTRL_DR_SHIFT 14
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#define MX27_CSPICTRL_DR_SHIFT 14
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#define MX27_CSPICTRL_CS_SHIFT 19
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#define MX27_CSPICTRL_CS_SHIFT 19
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-static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
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+static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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{
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unsigned int val = 0;
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unsigned int val = 0;
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@@ -262,7 +276,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
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writel(val, spi_imx->base + MXC_CSPIINT);
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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}
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-static void mx27_trigger(struct spi_imx_data *spi_imx)
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+static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
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{
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{
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unsigned int reg;
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unsigned int reg;
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@@ -271,7 +285,7 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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}
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-static int mx27_config(struct spi_imx_data *spi_imx,
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+static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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struct spi_imx_config *config)
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{
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{
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unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
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unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
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@@ -294,7 +308,7 @@ static int mx27_config(struct spi_imx_data *spi_imx,
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return 0;
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return 0;
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}
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}
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-static int mx27_rx_available(struct spi_imx_data *spi_imx)
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+static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
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{
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{
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return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
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return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
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}
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}
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@@ -310,7 +324,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
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#define MX1_CSPICTRL_MASTER (1 << 10)
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#define MX1_CSPICTRL_MASTER (1 << 10)
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#define MX1_CSPICTRL_DR_SHIFT 13
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#define MX1_CSPICTRL_DR_SHIFT 13
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-static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
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+static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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{
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unsigned int val = 0;
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unsigned int val = 0;
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@@ -322,7 +336,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
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writel(val, spi_imx->base + MXC_CSPIINT);
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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}
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-static void mx1_trigger(struct spi_imx_data *spi_imx)
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+static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
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{
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{
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unsigned int reg;
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unsigned int reg;
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@@ -331,7 +345,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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}
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-static int mx1_config(struct spi_imx_data *spi_imx,
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+static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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struct spi_imx_config *config)
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{
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{
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unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
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unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
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@@ -350,11 +364,50 @@ static int mx1_config(struct spi_imx_data *spi_imx,
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return 0;
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return 0;
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}
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}
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-static int mx1_rx_available(struct spi_imx_data *spi_imx)
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+static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
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{
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{
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return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
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return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
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}
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}
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+/*
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+ * These version numbers are taken from the Freescale driver. Unfortunately it
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+ * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
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+ */
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+static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
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+#ifdef CONFIG_SPI_IMX_VER_IMX1
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+ [SPI_IMX_VER_IMX1] = {
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+ .intctrl = mx1_intctrl,
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+ .config = mx1_config,
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+ .trigger = mx1_trigger,
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+ .rx_available = mx1_rx_available,
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+ },
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+#endif
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+#ifdef CONFIG_SPI_IMX_VER_0_0
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+ [SPI_IMX_VER_0_0] = {
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+ .intctrl = mx27_intctrl,
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+ .config = mx27_config,
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+ .trigger = mx27_trigger,
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+ .rx_available = mx27_rx_available,
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+ },
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+#endif
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+#ifdef CONFIG_SPI_IMX_VER_0_4
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+ [SPI_IMX_VER_0_4] = {
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+ .intctrl = mx31_intctrl,
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+ .config = mx31_config,
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+ .trigger = mx31_trigger,
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+ .rx_available = mx31_rx_available,
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+ },
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+#endif
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+#ifdef CONFIG_SPI_IMX_VER_0_7
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+ [SPI_IMX_VER_0_7] = {
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+ .intctrl = mx31_intctrl,
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+ .config = mx31_config,
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+ .trigger = mx31_trigger,
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+ .rx_available = mx31_rx_available,
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+ },
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+#endif
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+};
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+
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static void spi_imx_chipselect(struct spi_device *spi, int is_active)
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static void spi_imx_chipselect(struct spi_device *spi, int is_active)
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{
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{
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
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@@ -377,14 +430,14 @@ static void spi_imx_push(struct spi_imx_data *spi_imx)
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spi_imx->txfifo++;
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spi_imx->txfifo++;
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}
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}
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- spi_imx->trigger(spi_imx);
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+ spi_imx->devtype_data.trigger(spi_imx);
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}
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}
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static irqreturn_t spi_imx_isr(int irq, void *dev_id)
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static irqreturn_t spi_imx_isr(int irq, void *dev_id)
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{
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{
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struct spi_imx_data *spi_imx = dev_id;
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struct spi_imx_data *spi_imx = dev_id;
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- while (spi_imx->rx_available(spi_imx)) {
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+ while (spi_imx->devtype_data.rx_available(spi_imx)) {
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spi_imx->rx(spi_imx);
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spi_imx->rx(spi_imx);
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spi_imx->txfifo--;
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spi_imx->txfifo--;
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}
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}
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@@ -398,11 +451,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
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/* No data left to push, but still waiting for rx data,
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/* No data left to push, but still waiting for rx data,
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* enable receive data available interrupt.
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* enable receive data available interrupt.
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*/
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*/
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- spi_imx->intctrl(spi_imx, MXC_INT_RR);
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+ spi_imx->devtype_data.intctrl(
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+ spi_imx, MXC_INT_RR);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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- spi_imx->intctrl(spi_imx, 0);
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+ spi_imx->devtype_data.intctrl(spi_imx, 0);
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complete(&spi_imx->xfer_done);
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complete(&spi_imx->xfer_done);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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@@ -439,7 +493,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
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} else
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} else
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BUG();
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BUG();
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- spi_imx->config(spi_imx, &config);
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+ spi_imx->devtype_data.config(spi_imx, &config);
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return 0;
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return 0;
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}
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}
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@@ -458,7 +512,7 @@ static int spi_imx_transfer(struct spi_device *spi,
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spi_imx_push(spi_imx);
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spi_imx_push(spi_imx);
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- spi_imx->intctrl(spi_imx, MXC_INT_TE);
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+ spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
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wait_for_completion(&spi_imx->xfer_done);
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wait_for_completion(&spi_imx->xfer_done);
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@@ -485,6 +539,33 @@ static void spi_imx_cleanup(struct spi_device *spi)
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{
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{
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}
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}
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+static struct platform_device_id spi_imx_devtype[] = {
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+ {
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+ .name = DRIVER_NAME,
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+ .driver_data = SPI_IMX_VER_AUTODETECT,
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+ }, {
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+ .name = "imx1-cspi",
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+ .driver_data = SPI_IMX_VER_IMX1,
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+ }, {
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+ .name = "imx21-cspi",
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+ .driver_data = SPI_IMX_VER_0_0,
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+ }, {
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+ .name = "imx25-cspi",
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+ .driver_data = SPI_IMX_VER_0_7,
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+ }, {
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+ .name = "imx27-cspi",
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+ .driver_data = SPI_IMX_VER_0_0,
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+ }, {
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+ .name = "imx31-cspi",
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+ .driver_data = SPI_IMX_VER_0_4,
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+ }, {
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+ .name = "imx35-cspi",
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+ .driver_data = SPI_IMX_VER_0_7,
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+ }, {
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+ /* sentinel */
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+ }
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+};
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+
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static int __devinit spi_imx_probe(struct platform_device *pdev)
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static int __devinit spi_imx_probe(struct platform_device *pdev)
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{
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{
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struct spi_imx_master *mxc_platform_info;
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struct spi_imx_master *mxc_platform_info;
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@@ -536,6 +617,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
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init_completion(&spi_imx->xfer_done);
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init_completion(&spi_imx->xfer_done);
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+ if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
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+ if (cpu_is_mx25() || cpu_is_mx35())
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+ spi_imx->devtype_data =
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+ spi_imx_devtype_data[SPI_IMX_VER_0_7];
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+ else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
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+ spi_imx->devtype_data =
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+ spi_imx_devtype_data[SPI_IMX_VER_0_4];
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+ else if (cpu_is_mx27() || cpu_is_mx21())
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+ spi_imx->devtype_data =
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+ spi_imx_devtype_data[SPI_IMX_VER_0_0];
|
|
|
|
+ else if (cpu_is_mx1())
|
|
|
|
+ spi_imx->devtype_data =
|
|
|
|
+ spi_imx_devtype_data[SPI_IMX_VER_IMX1];
|
|
|
|
+ else
|
|
|
|
+ BUG();
|
|
|
|
+ } else
|
|
|
|
+ spi_imx->devtype_data =
|
|
|
|
+ spi_imx_devtype_data[pdev->id_entry->driver_data];
|
|
|
|
+
|
|
|
|
+ if (!spi_imx->devtype_data.intctrl) {
|
|
|
|
+ dev_err(&pdev->dev, "no support for this device compiled in\n");
|
|
|
|
+ ret = -ENODEV;
|
|
|
|
+ goto out_gpio_free;
|
|
|
|
+ }
|
|
|
|
+
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "can't get platform resource\n");
|
|
dev_err(&pdev->dev, "can't get platform resource\n");
|
|
@@ -567,24 +673,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|
goto out_iounmap;
|
|
goto out_iounmap;
|
|
}
|
|
}
|
|
|
|
|
|
- if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
|
|
|
|
- spi_imx->intctrl = mx31_intctrl;
|
|
|
|
- spi_imx->config = mx31_config;
|
|
|
|
- spi_imx->trigger = mx31_trigger;
|
|
|
|
- spi_imx->rx_available = mx31_rx_available;
|
|
|
|
- } else if (cpu_is_mx27() || cpu_is_mx21()) {
|
|
|
|
- spi_imx->intctrl = mx27_intctrl;
|
|
|
|
- spi_imx->config = mx27_config;
|
|
|
|
- spi_imx->trigger = mx27_trigger;
|
|
|
|
- spi_imx->rx_available = mx27_rx_available;
|
|
|
|
- } else if (cpu_is_mx1()) {
|
|
|
|
- spi_imx->intctrl = mx1_intctrl;
|
|
|
|
- spi_imx->config = mx1_config;
|
|
|
|
- spi_imx->trigger = mx1_trigger;
|
|
|
|
- spi_imx->rx_available = mx1_rx_available;
|
|
|
|
- } else
|
|
|
|
- BUG();
|
|
|
|
-
|
|
|
|
spi_imx->clk = clk_get(&pdev->dev, NULL);
|
|
spi_imx->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(spi_imx->clk)) {
|
|
if (IS_ERR(spi_imx->clk)) {
|
|
dev_err(&pdev->dev, "unable to get clock\n");
|
|
dev_err(&pdev->dev, "unable to get clock\n");
|
|
@@ -603,7 +691,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|
while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
|
|
while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
|
|
readl(spi_imx->base + MXC_CSPIRXDATA);
|
|
readl(spi_imx->base + MXC_CSPIRXDATA);
|
|
|
|
|
|
- spi_imx->intctrl(spi_imx, 0);
|
|
|
|
|
|
+ spi_imx->devtype_data.intctrl(spi_imx, 0);
|
|
|
|
|
|
ret = spi_bitbang_start(&spi_imx->bitbang);
|
|
ret = spi_bitbang_start(&spi_imx->bitbang);
|
|
if (ret) {
|
|
if (ret) {
|
|
@@ -668,6 +756,7 @@ static struct platform_driver spi_imx_driver = {
|
|
.name = DRIVER_NAME,
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
},
|
|
|
|
+ .id_table = spi_imx_devtype,
|
|
.probe = spi_imx_probe,
|
|
.probe = spi_imx_probe,
|
|
.remove = __devexit_p(spi_imx_remove),
|
|
.remove = __devexit_p(spi_imx_remove),
|
|
};
|
|
};
|