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@@ -1276,44 +1276,17 @@ arch_initcall(cpm_smc_uart_of_init);
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#endif /* CONFIG_8xx */
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#endif /* CONFIG_PPC_CPM_NEW_BINDING */
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-int __init fsl_spi_init(struct spi_board_info *board_infos,
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- unsigned int num_board_infos,
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- void (*activate_cs)(u8 cs, u8 polarity),
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- void (*deactivate_cs)(u8 cs, u8 polarity))
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+static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
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+ struct spi_board_info *board_infos,
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+ unsigned int num_board_infos,
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+ void (*activate_cs)(u8 cs, u8 polarity),
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+ void (*deactivate_cs)(u8 cs, u8 polarity))
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{
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struct device_node *np;
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- unsigned int i;
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- u32 sysclk = -1;
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-
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- /* SPI controller is either clocked from QE or SoC clock */
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-#ifdef CONFIG_QUICC_ENGINE
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- sysclk = get_brgfreq();
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-#endif
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- if (sysclk == -1) {
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- const u32 *freq;
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- int size;
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-
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- np = of_find_node_by_type(NULL, "soc");
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- if (!np)
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- return -ENODEV;
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-
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- freq = of_get_property(np, "clock-frequency", &size);
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- if (!freq || size != sizeof(*freq) || *freq == 0) {
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- freq = of_get_property(np, "bus-frequency", &size);
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- if (!freq || size != sizeof(*freq) || *freq == 0) {
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- of_node_put(np);
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- return -ENODEV;
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- }
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- }
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-
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- sysclk = *freq;
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- of_node_put(np);
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- }
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+ unsigned int i = 0;
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- for (np = NULL, i = 1;
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- (np = of_find_compatible_node(np, "spi", "fsl_spi")) != NULL;
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- i++) {
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- int ret = 0;
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+ for_each_compatible_node(np, type, compatible) {
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+ int ret;
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unsigned int j;
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const void *prop;
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struct resource res[2];
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@@ -1332,6 +1305,10 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
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goto err;
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pdata.bus_num = *(u32 *)prop;
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+ prop = of_get_property(np, "cell-index", NULL);
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+ if (prop)
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+ i = *(u32 *)prop;
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+
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prop = of_get_property(np, "mode", NULL);
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if (prop && !strcmp(prop, "cpu-qe"))
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pdata.qe_mode = 1;
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@@ -1342,7 +1319,7 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
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}
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if (!pdata.max_chipselect)
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- goto err;
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+ continue;
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ret = of_address_to_resource(np, 0, &res[0]);
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if (ret)
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@@ -1369,13 +1346,58 @@ int __init fsl_spi_init(struct spi_board_info *board_infos,
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if (ret)
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goto unreg;
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- continue;
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+ goto next;
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unreg:
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platform_device_del(pdev);
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err:
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- continue;
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+ pr_err("%s: registration failed\n", np->full_name);
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+next:
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+ i++;
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}
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+ return i;
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+}
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+
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+int __init fsl_spi_init(struct spi_board_info *board_infos,
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+ unsigned int num_board_infos,
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+ void (*activate_cs)(u8 cs, u8 polarity),
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+ void (*deactivate_cs)(u8 cs, u8 polarity))
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+{
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+ u32 sysclk = -1;
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+ int ret;
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+
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+#ifdef CONFIG_QUICC_ENGINE
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+ /* SPI controller is either clocked from QE or SoC clock */
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+ sysclk = get_brgfreq();
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+#endif
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+ if (sysclk == -1) {
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+ struct device_node *np;
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+ const u32 *freq;
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+ int size;
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+
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+ np = of_find_node_by_type(NULL, "soc");
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+ if (!np)
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+ return -ENODEV;
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+
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+ freq = of_get_property(np, "clock-frequency", &size);
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+ if (!freq || size != sizeof(*freq) || *freq == 0) {
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+ freq = of_get_property(np, "bus-frequency", &size);
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+ if (!freq || size != sizeof(*freq) || *freq == 0) {
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+ of_node_put(np);
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+ return -ENODEV;
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+ }
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+ }
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+
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+ sysclk = *freq;
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+ of_node_put(np);
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+ }
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+
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+ ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
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+ num_board_infos, activate_cs, deactivate_cs);
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+ if (!ret)
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+ of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
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+ num_board_infos, activate_cs, deactivate_cs);
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+
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return spi_register_board_info(board_infos, num_board_infos);
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}
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