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@@ -3,11 +3,12 @@
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*
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* SDRAM timing related functions for OMAP2xxx
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*
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- * Copyright (C) 2005 Texas Instruments Inc.
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- * Richard Woodruff <r-woodruff2@ti.com>
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+ * Copyright (C) 2005, 2008 Texas Instruments Inc.
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+ * Copyright (C) 2005, 2008 Nokia Corporation
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*
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- * Copyright (C) 2005 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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+ * Paul Walmsley
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+ * Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@@ -39,23 +40,20 @@
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#define M_LOCK 1
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-void __iomem *omap2_sdrc_base;
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-void __iomem *omap2_sms_base;
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-
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static struct memory_timings mem_timings;
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static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
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-u32 omap2_memory_get_slow_dll_ctrl(void)
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+static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
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{
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return mem_timings.slow_dll_ctrl;
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}
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-u32 omap2_memory_get_fast_dll_ctrl(void)
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+static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
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{
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return mem_timings.fast_dll_ctrl;
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}
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-u32 omap2_memory_get_type(void)
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+static u32 omap2xxx_sdrc_get_type(void)
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{
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return mem_timings.m_type;
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}
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@@ -64,7 +62,7 @@ u32 omap2_memory_get_type(void)
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* Check the DLL lock state, and return tue if running in unlock mode.
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* This is needed to compensate for the shifted DLL value in unlock mode.
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*/
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-u32 omap2_dll_force_needed(void)
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+u32 omap2xxx_sdrc_dll_is_unlocked(void)
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{
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/* dlla and dllb are a set */
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u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
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@@ -79,8 +77,10 @@ u32 omap2_dll_force_needed(void)
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* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
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* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
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* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
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+ *
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+ * Used by the clock framework during CORE DPLL changes
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*/
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-u32 omap2_reprogram_sdrc(u32 level, u32 force)
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+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
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{
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u32 dll_ctrl, m_type;
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u32 prev = curr_perf_level;
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@@ -90,13 +90,13 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
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return prev;
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if (level == CORE_CLK_SRC_DPLL)
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- dll_ctrl = omap2_memory_get_slow_dll_ctrl();
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+ dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
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else if (level == CORE_CLK_SRC_DPLL_X2)
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- dll_ctrl = omap2_memory_get_fast_dll_ctrl();
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+ dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
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else
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return prev;
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- m_type = omap2_memory_get_type();
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+ m_type = omap2xxx_sdrc_get_type();
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local_irq_save(flags);
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__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
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@@ -107,18 +107,8 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
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return prev;
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}
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-#if !defined(CONFIG_ARCH_OMAP2)
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-void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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- u32 base_cs, u32 force_unlock)
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-{
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-}
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-void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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- u32 mem_type)
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-{
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-}
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-#endif
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-
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-void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
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+/* Used by the clock framework during CORE DPLL changes */
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+void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
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{
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unsigned long dll_cnt;
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u32 fast_dll = 0;
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@@ -171,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
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/* 90 degree phase for anything below 133Mhz + disable DLL filter */
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mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
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}
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-
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-void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
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-{
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- omap2_sdrc_base = omap2_globals->sdrc;
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- omap2_sms_base = omap2_globals->sms;
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-}
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-
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-/* turn on smart idle modes for SDRAM scheduler and controller */
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-void __init omap2_init_memory(void)
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-{
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- u32 l;
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-
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- if (!cpu_is_omap2420())
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- return;
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-
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- l = sms_read_reg(SMS_SYSCONFIG);
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- l &= ~(0x3 << 3);
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- l |= (0x2 << 3);
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- sms_write_reg(l, SMS_SYSCONFIG);
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-
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- l = sdrc_read_reg(SDRC_SYSCONFIG);
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- l &= ~(0x3 << 3);
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- l |= (0x2 << 3);
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- sdrc_write_reg(l, SDRC_SYSCONFIG);
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-}
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Paul Walmsley