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@@ -1,7 +1,7 @@
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/*
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- * linux/arch/arm/mach-omap2/memory.c
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+ * linux/arch/arm/mach-omap2/sdrc2xxx.c
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*
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- * Memory timing related functions for OMAP24XX
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+ * SDRAM timing related functions for OMAP2xxx
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*
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* Copyright (C) 2005 Texas Instruments Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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@@ -89,13 +89,12 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
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if ((curr_perf_level == level) && !force)
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return prev;
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- if (level == CORE_CLK_SRC_DPLL) {
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+ if (level == CORE_CLK_SRC_DPLL)
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dll_ctrl = omap2_memory_get_slow_dll_ctrl();
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- } else if (level == CORE_CLK_SRC_DPLL_X2) {
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+ else if (level == CORE_CLK_SRC_DPLL_X2)
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dll_ctrl = omap2_memory_get_fast_dll_ctrl();
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- } else {
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+ else
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return prev;
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- }
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m_type = omap2_memory_get_type();
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@@ -124,7 +123,8 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
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unsigned long dll_cnt;
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u32 fast_dll = 0;
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- mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
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+ /* DDR = 1, SDR = 0 */
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+ mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
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/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
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* In the case of 2422, its ok to use CS1 instead of CS0.
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