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@@ -10,6 +10,20 @@
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#include "qlcnic_83xx_hw.h"
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#include <linux/types.h>
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+#define QLC_BC_COMMAND 0
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+#define QLC_BC_RESPONSE 1
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+
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+#define QLC_MBOX_RESP_TIMEOUT (10 * HZ)
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+#define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ)
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+
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+#define QLC_BC_MSG 0
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+#define QLC_BC_CFREE 1
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+#define QLC_BC_HDR_SZ 16
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+#define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ)
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+
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+static int qlcnic_sriov_vf_mbx_op(struct qlcnic_adapter *,
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+ struct qlcnic_cmd_args *);
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+
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static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
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.read_crb = qlcnic_83xx_read_crb,
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.write_crb = qlcnic_83xx_write_crb,
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@@ -18,6 +32,7 @@ static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = {
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.get_mac_address = qlcnic_83xx_get_mac_address,
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.setup_intr = qlcnic_83xx_setup_intr,
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.alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
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+ .mbx_cmd = qlcnic_sriov_vf_mbx_op,
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.get_func_no = qlcnic_83xx_get_func_no,
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.api_lock = qlcnic_83xx_cam_lock,
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.api_unlock = qlcnic_83xx_cam_unlock,
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@@ -49,9 +64,50 @@ static struct qlcnic_nic_template qlcnic_sriov_vf_ops = {
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.clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
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};
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+static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = {
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+ {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2},
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+ {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2},
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+};
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+
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+static inline bool qlcnic_sriov_bc_msg_check(u32 val)
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+{
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+ return (val & (1 << QLC_BC_MSG)) ? true : false;
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+}
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+
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+static inline bool qlcnic_sriov_channel_free_check(u32 val)
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+{
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+ return (val & (1 << QLC_BC_CFREE)) ? true : false;
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+}
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+
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+static inline u8 qlcnic_sriov_target_func_id(u32 val)
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+{
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+ return (val >> 4) & 0xff;
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+}
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+
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+static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id)
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+{
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+ struct pci_dev *dev = adapter->pdev;
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+ int pos;
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+ u16 stride, offset;
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+
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+ if (qlcnic_sriov_vf_check(adapter))
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+ return 0;
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+
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
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+ pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
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+ pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
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+
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+ return (dev->devfn + offset + stride * vf_id) & 0xff;
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+}
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+
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int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
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{
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struct qlcnic_sriov *sriov;
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+ struct qlcnic_back_channel *bc;
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+ struct workqueue_struct *wq;
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+ struct qlcnic_vport *vp;
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+ struct qlcnic_vf_info *vf;
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+ int err, i;
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if (!qlcnic_sriov_enable_check(adapter))
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return -EIO;
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@@ -62,19 +118,84 @@ int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs)
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adapter->ahw->sriov = sriov;
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sriov->num_vfs = num_vfs;
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+ bc = &sriov->bc;
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+ sriov->vf_info = kzalloc(sizeof(struct qlcnic_vf_info) *
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+ num_vfs, GFP_KERNEL);
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+ if (!sriov->vf_info) {
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+ err = -ENOMEM;
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+ goto qlcnic_free_sriov;
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+ }
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+
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+ wq = create_singlethread_workqueue("bc-trans");
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+ if (wq == NULL) {
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+ err = -ENOMEM;
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+ dev_err(&adapter->pdev->dev,
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+ "Cannot create bc-trans workqueue\n");
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+ goto qlcnic_free_vf_info;
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+ }
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+
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+ bc->bc_trans_wq = wq;
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+
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+ for (i = 0; i < num_vfs; i++) {
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+ vf = &sriov->vf_info[i];
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+ vf->adapter = adapter;
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+ vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i);
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+ mutex_init(&vf->send_cmd_lock);
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+ INIT_LIST_HEAD(&vf->rcv_act.wait_list);
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+ INIT_LIST_HEAD(&vf->rcv_pend.wait_list);
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+ spin_lock_init(&vf->rcv_act.lock);
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+ spin_lock_init(&vf->rcv_pend.lock);
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+ init_completion(&vf->ch_free_cmpl);
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+
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+ if (qlcnic_sriov_pf_check(adapter)) {
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+ vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL);
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+ if (!vp) {
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+ err = -ENOMEM;
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+ goto qlcnic_destroy_trans_wq;
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+ }
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+ sriov->vf_info[i].vp = vp;
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+ random_ether_addr(vp->mac);
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+ dev_info(&adapter->pdev->dev,
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+ "MAC Address %pM is configured for VF %d\n",
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+ vp->mac, i);
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+ }
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+ }
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+
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return 0;
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+
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+qlcnic_destroy_trans_wq:
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+ destroy_workqueue(bc->bc_trans_wq);
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+
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+qlcnic_free_vf_info:
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+ kfree(sriov->vf_info);
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+
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+qlcnic_free_sriov:
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+ kfree(adapter->ahw->sriov);
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+ return err;
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}
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void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
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{
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+ struct qlcnic_sriov *sriov = adapter->ahw->sriov;
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+ struct qlcnic_back_channel *bc = &sriov->bc;
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+ int i;
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+
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if (!qlcnic_sriov_enable_check(adapter))
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return;
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+ destroy_workqueue(bc->bc_trans_wq);
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+
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+ for (i = 0; i < sriov->num_vfs; i++)
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+ kfree(sriov->vf_info[i].vp);
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+
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+ kfree(sriov->vf_info);
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kfree(adapter->ahw->sriov);
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}
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static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter)
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{
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+ qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
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+ qlcnic_sriov_cfg_bc_intr(adapter, 0);
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__qlcnic_sriov_cleanup(adapter);
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}
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@@ -87,6 +208,103 @@ void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter)
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qlcnic_sriov_vf_cleanup(adapter);
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}
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+static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr,
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+ u32 *pay, u8 pci_func, u8 size)
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+{
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+ struct qlcnic_hardware_context *ahw = adapter->ahw;
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+ unsigned long flags;
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+ u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd, val;
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+ u16 opcode;
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+ u8 mbx_err_code;
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+ int i, j;
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+
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+ opcode = ((struct qlcnic_bc_hdr *)hdr)->cmd_op;
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+
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+ if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
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+ dev_info(&adapter->pdev->dev,
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+ "Mailbox cmd attempted, 0x%x\n", opcode);
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+ dev_info(&adapter->pdev->dev, "Mailbox detached\n");
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+ return 0;
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+ }
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+
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+ spin_lock_irqsave(&ahw->mbx_lock, flags);
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+
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+ mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
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+ if (mbx_val) {
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+ QLCDB(adapter, DRV, "Mailbox cmd attempted, 0x%x\n", opcode);
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+ spin_unlock_irqrestore(&ahw->mbx_lock, flags);
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+ return QLCNIC_RCODE_TIMEOUT;
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+ }
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+ /* Fill in mailbox registers */
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+ val = size + (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
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+ mbx_cmd = 0x31 | (val << 16) | (adapter->ahw->fw_hal_version << 29);
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+
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+ writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
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+ mbx_cmd = 0x1 | (1 << 4);
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+
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+ if (qlcnic_sriov_pf_check(adapter))
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+ mbx_cmd |= (pci_func << 5);
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+
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+ writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
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+ for (i = 2, j = 0; j < (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
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+ i++, j++) {
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+ writel(*(hdr++), QLCNIC_MBX_HOST(ahw, i));
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+ }
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+ for (j = 0; j < size; j++, i++)
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+ writel(*(pay++), QLCNIC_MBX_HOST(ahw, i));
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+
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+ /* Signal FW about the impending command */
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+ QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
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+
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+ /* Waiting for the mailbox cmd to complete and while waiting here
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+ * some AEN might arrive. If more than 5 seconds expire we can
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+ * assume something is wrong.
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+ */
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+poll:
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+ rsp = qlcnic_83xx_mbx_poll(adapter);
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+ if (rsp != QLCNIC_RCODE_TIMEOUT) {
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+ /* Get the FW response data */
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+ fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
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+ if (fw_data & QLCNIC_MBX_ASYNC_EVENT) {
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+ qlcnic_83xx_process_aen(adapter);
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+ mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
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+ if (mbx_val)
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+ goto poll;
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+ }
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+ mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
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+ rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
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+ opcode = QLCNIC_MBX_RSP(fw_data);
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+
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+ switch (mbx_err_code) {
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+ case QLCNIC_MBX_RSP_OK:
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+ case QLCNIC_MBX_PORT_RSP_OK:
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+ rsp = QLCNIC_RCODE_SUCCESS;
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+ break;
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+ default:
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+ if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
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+ rsp = qlcnic_83xx_mac_rcode(adapter);
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+ if (!rsp)
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+ goto out;
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+ }
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+ dev_err(&adapter->pdev->dev,
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+ "MBX command 0x%x failed with err:0x%x\n",
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+ opcode, mbx_err_code);
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+ rsp = mbx_err_code;
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+ break;
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+ }
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+ goto out;
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+ }
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+
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+ dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
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+ QLCNIC_MBX_RSP(mbx_cmd));
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+ rsp = QLCNIC_RCODE_TIMEOUT;
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+out:
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+ /* clear fw mbx control register */
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+ QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
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+ spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
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+ return rsp;
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+}
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+
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static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
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int pci_using_dac)
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{
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@@ -110,15 +328,29 @@ static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter,
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if (err)
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goto err_out_disable_mbx_intr;
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- err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
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+ err = qlcnic_sriov_cfg_bc_intr(adapter, 1);
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if (err)
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goto err_out_cleanup_sriov;
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+ err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT);
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+ if (err)
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+ goto err_out_disable_bc_intr;
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+
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+ err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac);
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+ if (err)
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+ goto err_out_send_channel_term;
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+
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pci_set_drvdata(adapter->pdev, adapter);
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dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
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adapter->netdev->name);
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return 0;
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+err_out_send_channel_term:
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+ qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM);
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+
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+err_out_disable_bc_intr:
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+ qlcnic_sriov_cfg_bc_intr(adapter, 0);
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+
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err_out_cleanup_sriov:
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__qlcnic_sriov_cleanup(adapter);
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@@ -173,3 +405,720 @@ void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw)
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ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
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ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
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}
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+
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+static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag)
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+{
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+ u32 pay_size;
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+
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+ pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ);
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+
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+ if (pay_size)
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+ pay_size = QLC_BC_PAYLOAD_SZ;
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+ else
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+ pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ;
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+
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+ return pay_size;
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+}
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+
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+int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func)
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+{
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+ struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info;
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+ u8 i;
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+
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+ if (qlcnic_sriov_vf_check(adapter))
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+ return 0;
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+
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+ for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) {
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+ if (vf_info[i].pci_func == pci_func)
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+ return i;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans)
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+{
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+ *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC);
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+ if (!*trans)
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+ return -ENOMEM;
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+
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+ init_completion(&(*trans)->resp_cmpl);
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+ return 0;
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+}
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+
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+static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr,
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+ u32 size)
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+{
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+ *hdr = kzalloc(sizeof(struct qlcnic_bc_hdr) * size, GFP_ATOMIC);
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+ if (!*hdr)
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+ return -ENOMEM;
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+
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+ return 0;
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+}
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+
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+static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type)
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+{
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+ const struct qlcnic_mailbox_metadata *mbx_tbl;
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+ int i, size;
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+
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+ mbx_tbl = qlcnic_sriov_bc_mbx_tbl;
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+ size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl);
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+
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+ for (i = 0; i < size; i++) {
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+ if (type == mbx_tbl[i].cmd) {
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+ mbx->op_type = QLC_BC_CMD;
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+ mbx->req.num = mbx_tbl[i].in_args;
|
|
|
+ mbx->rsp.num = mbx_tbl[i].out_args;
|
|
|
+ mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
|
|
|
+ GFP_ATOMIC);
|
|
|
+ if (!mbx->req.arg)
|
|
|
+ return -ENOMEM;
|
|
|
+ mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
|
|
|
+ GFP_ATOMIC);
|
|
|
+ if (!mbx->rsp.arg) {
|
|
|
+ kfree(mbx->req.arg);
|
|
|
+ mbx->req.arg = NULL;
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
|
|
|
+ memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
|
|
|
+ mbx->req.arg[0] = (type | (mbx->req.num << 16) |
|
|
|
+ (3 << 29));
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans,
|
|
|
+ struct qlcnic_cmd_args *cmd,
|
|
|
+ u16 seq, u8 msg_type)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_hdr *hdr;
|
|
|
+ int i;
|
|
|
+ u32 num_regs, bc_pay_sz;
|
|
|
+ u16 remainder;
|
|
|
+ u8 cmd_op, num_frags, t_num_frags;
|
|
|
+
|
|
|
+ bc_pay_sz = QLC_BC_PAYLOAD_SZ;
|
|
|
+ if (msg_type == QLC_BC_COMMAND) {
|
|
|
+ trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg;
|
|
|
+ trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg;
|
|
|
+ num_regs = cmd->req.num;
|
|
|
+ trans->req_pay_size = (num_regs * 4);
|
|
|
+ num_regs = cmd->rsp.num;
|
|
|
+ trans->rsp_pay_size = (num_regs * 4);
|
|
|
+ cmd_op = cmd->req.arg[0] & 0xff;
|
|
|
+ remainder = (trans->req_pay_size) % (bc_pay_sz);
|
|
|
+ num_frags = (trans->req_pay_size) / (bc_pay_sz);
|
|
|
+ if (remainder)
|
|
|
+ num_frags++;
|
|
|
+ t_num_frags = num_frags;
|
|
|
+ if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags))
|
|
|
+ return -ENOMEM;
|
|
|
+ remainder = (trans->rsp_pay_size) % (bc_pay_sz);
|
|
|
+ num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
|
|
|
+ if (remainder)
|
|
|
+ num_frags++;
|
|
|
+ if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags))
|
|
|
+ return -ENOMEM;
|
|
|
+ num_frags = t_num_frags;
|
|
|
+ hdr = trans->req_hdr;
|
|
|
+ } else {
|
|
|
+ cmd->req.arg = (u32 *)trans->req_pay;
|
|
|
+ cmd->rsp.arg = (u32 *)trans->rsp_pay;
|
|
|
+ cmd_op = cmd->req.arg[0] & 0xff;
|
|
|
+ remainder = (trans->rsp_pay_size) % (bc_pay_sz);
|
|
|
+ num_frags = (trans->rsp_pay_size) / (bc_pay_sz);
|
|
|
+ if (remainder)
|
|
|
+ num_frags++;
|
|
|
+ cmd->req.num = trans->req_pay_size / 4;
|
|
|
+ cmd->rsp.num = trans->rsp_pay_size / 4;
|
|
|
+ hdr = trans->rsp_hdr;
|
|
|
+ }
|
|
|
+
|
|
|
+ trans->trans_id = seq;
|
|
|
+ trans->cmd_id = cmd_op;
|
|
|
+ for (i = 0; i < num_frags; i++) {
|
|
|
+ hdr[i].version = 2;
|
|
|
+ hdr[i].msg_type = msg_type;
|
|
|
+ hdr[i].op_type = cmd->op_type;
|
|
|
+ hdr[i].num_cmds = 1;
|
|
|
+ hdr[i].num_frags = num_frags;
|
|
|
+ hdr[i].frag_num = i + 1;
|
|
|
+ hdr[i].cmd_op = cmd_op;
|
|
|
+ hdr[i].seq_id = seq;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans)
|
|
|
+{
|
|
|
+ if (!trans)
|
|
|
+ return;
|
|
|
+ kfree(trans->req_hdr);
|
|
|
+ kfree(trans->rsp_hdr);
|
|
|
+ kfree(trans);
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf,
|
|
|
+ struct qlcnic_bc_trans *trans, u8 type)
|
|
|
+{
|
|
|
+ struct qlcnic_trans_list *t_list;
|
|
|
+ unsigned long flags;
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ if (type == QLC_BC_RESPONSE) {
|
|
|
+ t_list = &vf->rcv_act;
|
|
|
+ spin_lock_irqsave(&t_list->lock, flags);
|
|
|
+ t_list->count--;
|
|
|
+ list_del(&trans->list);
|
|
|
+ if (t_list->count > 0)
|
|
|
+ ret = 1;
|
|
|
+ spin_unlock_irqrestore(&t_list->lock, flags);
|
|
|
+ }
|
|
|
+ if (type == QLC_BC_COMMAND) {
|
|
|
+ while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
|
|
|
+ msleep(100);
|
|
|
+ vf->send_cmd = NULL;
|
|
|
+ clear_bit(QLC_BC_VF_SEND, &vf->state);
|
|
|
+ }
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov,
|
|
|
+ struct qlcnic_vf_info *vf,
|
|
|
+ work_func_t func)
|
|
|
+{
|
|
|
+ INIT_WORK(&vf->trans_work, func);
|
|
|
+ queue_work(sriov->bc.bc_trans_wq, &vf->trans_work);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans)
|
|
|
+{
|
|
|
+ struct completion *cmpl = &trans->resp_cmpl;
|
|
|
+
|
|
|
+ if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT))
|
|
|
+ trans->trans_state = QLC_END;
|
|
|
+ else
|
|
|
+ trans->trans_state = QLC_ABORT;
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans,
|
|
|
+ u8 type)
|
|
|
+{
|
|
|
+ if (type == QLC_BC_RESPONSE) {
|
|
|
+ trans->curr_rsp_frag++;
|
|
|
+ if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
|
|
|
+ trans->trans_state = QLC_INIT;
|
|
|
+ else
|
|
|
+ trans->trans_state = QLC_END;
|
|
|
+ } else {
|
|
|
+ trans->curr_req_frag++;
|
|
|
+ if (trans->curr_req_frag < trans->req_hdr->num_frags)
|
|
|
+ trans->trans_state = QLC_INIT;
|
|
|
+ else
|
|
|
+ trans->trans_state = QLC_WAIT_FOR_RESP;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans,
|
|
|
+ u8 type)
|
|
|
+{
|
|
|
+ struct qlcnic_vf_info *vf = trans->vf;
|
|
|
+ struct completion *cmpl = &vf->ch_free_cmpl;
|
|
|
+
|
|
|
+ if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) {
|
|
|
+ trans->trans_state = QLC_ABORT;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
|
|
|
+ qlcnic_sriov_handle_multi_frags(trans, type);
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter,
|
|
|
+ u32 *hdr, u32 *pay, u32 size)
|
|
|
+{
|
|
|
+ struct qlcnic_hardware_context *ahw = adapter->ahw;
|
|
|
+ u32 fw_mbx;
|
|
|
+ u8 i, max = 2, hdr_size, j;
|
|
|
+
|
|
|
+ hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
|
|
|
+ max = (size / sizeof(u32)) + hdr_size;
|
|
|
+
|
|
|
+ fw_mbx = readl(QLCNIC_MBX_FW(ahw, 0));
|
|
|
+ for (i = 2, j = 0; j < hdr_size; i++, j++)
|
|
|
+ *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i));
|
|
|
+ for (; j < max; i++, j++)
|
|
|
+ *(pay++) = readl(QLCNIC_MBX_FW(ahw, i));
|
|
|
+}
|
|
|
+
|
|
|
+static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf)
|
|
|
+{
|
|
|
+ int ret = -EBUSY;
|
|
|
+ u32 timeout = 10000;
|
|
|
+
|
|
|
+ do {
|
|
|
+ if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) {
|
|
|
+ ret = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ mdelay(1);
|
|
|
+ } while (--timeout);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type)
|
|
|
+{
|
|
|
+ struct qlcnic_vf_info *vf = trans->vf;
|
|
|
+ u32 pay_size, hdr_size;
|
|
|
+ u32 *hdr, *pay;
|
|
|
+ int ret;
|
|
|
+ u8 pci_func = trans->func_id;
|
|
|
+
|
|
|
+ if (__qlcnic_sriov_issue_bc_post(vf))
|
|
|
+ return -EBUSY;
|
|
|
+
|
|
|
+ if (type == QLC_BC_COMMAND) {
|
|
|
+ hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag);
|
|
|
+ pay = (u32 *)(trans->req_pay + trans->curr_req_frag);
|
|
|
+ hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
|
|
|
+ pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
|
|
|
+ trans->curr_req_frag);
|
|
|
+ pay_size = (pay_size / sizeof(u32));
|
|
|
+ } else {
|
|
|
+ hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag);
|
|
|
+ pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag);
|
|
|
+ hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32));
|
|
|
+ pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
|
|
|
+ trans->curr_rsp_frag);
|
|
|
+ pay_size = (pay_size / sizeof(u32));
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay,
|
|
|
+ pci_func, pay_size);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans,
|
|
|
+ struct qlcnic_vf_info *vf, u8 type)
|
|
|
+{
|
|
|
+ int err;
|
|
|
+ bool flag = true;
|
|
|
+
|
|
|
+ while (flag) {
|
|
|
+ switch (trans->trans_state) {
|
|
|
+ case QLC_INIT:
|
|
|
+ trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE;
|
|
|
+ if (qlcnic_sriov_issue_bc_post(trans, type))
|
|
|
+ trans->trans_state = QLC_ABORT;
|
|
|
+ break;
|
|
|
+ case QLC_WAIT_FOR_CHANNEL_FREE:
|
|
|
+ qlcnic_sriov_wait_for_channel_free(trans, type);
|
|
|
+ break;
|
|
|
+ case QLC_WAIT_FOR_RESP:
|
|
|
+ qlcnic_sriov_wait_for_resp(trans);
|
|
|
+ break;
|
|
|
+ case QLC_END:
|
|
|
+ err = 0;
|
|
|
+ flag = false;
|
|
|
+ break;
|
|
|
+ case QLC_ABORT:
|
|
|
+ err = -EIO;
|
|
|
+ flag = false;
|
|
|
+ clear_bit(QLC_BC_VF_CHANNEL, &vf->state);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ err = -EIO;
|
|
|
+ flag = false;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter,
|
|
|
+ struct qlcnic_bc_trans *trans, int pci_func)
|
|
|
+{
|
|
|
+ struct qlcnic_vf_info *vf;
|
|
|
+ int err, index = qlcnic_sriov_func_to_index(adapter, pci_func);
|
|
|
+
|
|
|
+ if (index < 0)
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ vf = &adapter->ahw->sriov->vf_info[index];
|
|
|
+ trans->vf = vf;
|
|
|
+ trans->func_id = pci_func;
|
|
|
+
|
|
|
+ if (!test_bit(QLC_BC_VF_STATE, &vf->state)) {
|
|
|
+ if (qlcnic_sriov_pf_check(adapter))
|
|
|
+ return -EIO;
|
|
|
+ if (qlcnic_sriov_vf_check(adapter) &&
|
|
|
+ trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT)
|
|
|
+ return -EIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ mutex_lock(&vf->send_cmd_lock);
|
|
|
+ vf->send_cmd = trans;
|
|
|
+ err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND);
|
|
|
+ qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND);
|
|
|
+ mutex_unlock(&vf->send_cmd_lock);
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter,
|
|
|
+ struct qlcnic_bc_trans *trans,
|
|
|
+ struct qlcnic_cmd_args *cmd)
|
|
|
+{
|
|
|
+#ifdef CONFIG_QLCNIC_SRIOV
|
|
|
+ if (qlcnic_sriov_pf_check(adapter)) {
|
|
|
+ qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ cmd->rsp.arg[0] |= (0x9 << 25);
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_process_bc_cmd(struct work_struct *work)
|
|
|
+{
|
|
|
+ struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info,
|
|
|
+ trans_work);
|
|
|
+ struct qlcnic_bc_trans *trans = NULL;
|
|
|
+ struct qlcnic_adapter *adapter = vf->adapter;
|
|
|
+ struct qlcnic_cmd_args cmd;
|
|
|
+ u8 req;
|
|
|
+
|
|
|
+ trans = list_first_entry(&vf->rcv_act.wait_list,
|
|
|
+ struct qlcnic_bc_trans, list);
|
|
|
+ adapter = vf->adapter;
|
|
|
+
|
|
|
+ if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id,
|
|
|
+ QLC_BC_RESPONSE))
|
|
|
+ goto cleanup_trans;
|
|
|
+
|
|
|
+ __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd);
|
|
|
+ trans->trans_state = QLC_INIT;
|
|
|
+ __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE);
|
|
|
+
|
|
|
+cleanup_trans:
|
|
|
+ qlcnic_free_mbx_args(&cmd);
|
|
|
+ req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE);
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+ if (req)
|
|
|
+ qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf,
|
|
|
+ qlcnic_sriov_process_bc_cmd);
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr,
|
|
|
+ struct qlcnic_vf_info *vf)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_trans *trans;
|
|
|
+ u32 pay_size;
|
|
|
+
|
|
|
+ if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state))
|
|
|
+ return;
|
|
|
+
|
|
|
+ trans = vf->send_cmd;
|
|
|
+
|
|
|
+ if (trans == NULL)
|
|
|
+ goto clear_send;
|
|
|
+
|
|
|
+ if (trans->trans_id != hdr->seq_id)
|
|
|
+ goto clear_send;
|
|
|
+
|
|
|
+ pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size,
|
|
|
+ trans->curr_rsp_frag);
|
|
|
+ qlcnic_sriov_pull_bc_msg(vf->adapter,
|
|
|
+ (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag),
|
|
|
+ (u32 *)(trans->rsp_pay + trans->curr_rsp_frag),
|
|
|
+ pay_size);
|
|
|
+ if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags)
|
|
|
+ goto clear_send;
|
|
|
+
|
|
|
+ complete(&trans->resp_cmpl);
|
|
|
+
|
|
|
+clear_send:
|
|
|
+ clear_bit(QLC_BC_VF_SEND, &vf->state);
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov,
|
|
|
+ struct qlcnic_vf_info *vf,
|
|
|
+ struct qlcnic_bc_trans *trans)
|
|
|
+{
|
|
|
+ struct qlcnic_trans_list *t_list = &vf->rcv_act;
|
|
|
+
|
|
|
+ spin_lock(&t_list->lock);
|
|
|
+ t_list->count++;
|
|
|
+ list_add_tail(&trans->list, &t_list->wait_list);
|
|
|
+ if (t_list->count == 1)
|
|
|
+ qlcnic_sriov_schedule_bc_cmd(sriov, vf,
|
|
|
+ qlcnic_sriov_process_bc_cmd);
|
|
|
+ spin_unlock(&t_list->lock);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov,
|
|
|
+ struct qlcnic_vf_info *vf,
|
|
|
+ struct qlcnic_bc_hdr *hdr)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_trans *trans = NULL;
|
|
|
+ struct list_head *node;
|
|
|
+ u32 pay_size, curr_frag;
|
|
|
+ u8 found = 0, active = 0;
|
|
|
+
|
|
|
+ spin_lock(&vf->rcv_pend.lock);
|
|
|
+ if (vf->rcv_pend.count > 0) {
|
|
|
+ list_for_each(node, &vf->rcv_pend.wait_list) {
|
|
|
+ trans = list_entry(node, struct qlcnic_bc_trans, list);
|
|
|
+ if (trans->trans_id == hdr->seq_id) {
|
|
|
+ found = 1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (found) {
|
|
|
+ curr_frag = trans->curr_req_frag;
|
|
|
+ pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
|
|
|
+ curr_frag);
|
|
|
+ qlcnic_sriov_pull_bc_msg(vf->adapter,
|
|
|
+ (u32 *)(trans->req_hdr + curr_frag),
|
|
|
+ (u32 *)(trans->req_pay + curr_frag),
|
|
|
+ pay_size);
|
|
|
+ trans->curr_req_frag++;
|
|
|
+ if (trans->curr_req_frag >= hdr->num_frags) {
|
|
|
+ vf->rcv_pend.count--;
|
|
|
+ list_del(&trans->list);
|
|
|
+ active = 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ spin_unlock(&vf->rcv_pend.lock);
|
|
|
+
|
|
|
+ if (active)
|
|
|
+ if (qlcnic_sriov_add_act_list(sriov, vf, trans))
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov,
|
|
|
+ struct qlcnic_bc_hdr *hdr,
|
|
|
+ struct qlcnic_vf_info *vf)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_trans *trans;
|
|
|
+ struct qlcnic_adapter *adapter = vf->adapter;
|
|
|
+ struct qlcnic_cmd_args cmd;
|
|
|
+ u32 pay_size;
|
|
|
+ int err;
|
|
|
+ u8 cmd_op;
|
|
|
+
|
|
|
+ if (!test_bit(QLC_BC_VF_STATE, &vf->state) &&
|
|
|
+ hdr->op_type != QLC_BC_CMD &&
|
|
|
+ hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT)
|
|
|
+ return;
|
|
|
+
|
|
|
+ if (hdr->frag_num > 1) {
|
|
|
+ qlcnic_sriov_handle_pending_trans(sriov, vf, hdr);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cmd_op = hdr->cmd_op;
|
|
|
+ if (qlcnic_sriov_alloc_bc_trans(&trans))
|
|
|
+ return;
|
|
|
+
|
|
|
+ if (hdr->op_type == QLC_BC_CMD)
|
|
|
+ err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op);
|
|
|
+ else
|
|
|
+ err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op);
|
|
|
+
|
|
|
+ if (err) {
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ cmd.op_type = hdr->op_type;
|
|
|
+ if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id,
|
|
|
+ QLC_BC_COMMAND)) {
|
|
|
+ qlcnic_free_mbx_args(&cmd);
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size,
|
|
|
+ trans->curr_req_frag);
|
|
|
+ qlcnic_sriov_pull_bc_msg(vf->adapter,
|
|
|
+ (u32 *)(trans->req_hdr + trans->curr_req_frag),
|
|
|
+ (u32 *)(trans->req_pay + trans->curr_req_frag),
|
|
|
+ pay_size);
|
|
|
+ trans->func_id = vf->pci_func;
|
|
|
+ trans->vf = vf;
|
|
|
+ trans->trans_id = hdr->seq_id;
|
|
|
+ trans->curr_req_frag++;
|
|
|
+ if (trans->curr_req_frag == trans->req_hdr->num_frags) {
|
|
|
+ if (qlcnic_sriov_add_act_list(sriov, vf, trans)) {
|
|
|
+ qlcnic_free_mbx_args(&cmd);
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ spin_lock(&vf->rcv_pend.lock);
|
|
|
+ list_add_tail(&trans->list, &vf->rcv_pend.wait_list);
|
|
|
+ vf->rcv_pend.count++;
|
|
|
+ spin_unlock(&vf->rcv_pend.lock);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov,
|
|
|
+ struct qlcnic_vf_info *vf)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_hdr hdr;
|
|
|
+ u32 *ptr = (u32 *)&hdr;
|
|
|
+ u8 msg_type, i;
|
|
|
+
|
|
|
+ for (i = 2; i < 6; i++)
|
|
|
+ ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i));
|
|
|
+ msg_type = hdr.msg_type;
|
|
|
+
|
|
|
+ switch (msg_type) {
|
|
|
+ case QLC_BC_COMMAND:
|
|
|
+ qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf);
|
|
|
+ break;
|
|
|
+ case QLC_BC_RESPONSE:
|
|
|
+ qlcnic_sriov_handle_bc_resp(&hdr, vf);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event)
|
|
|
+{
|
|
|
+ struct qlcnic_vf_info *vf;
|
|
|
+ struct qlcnic_sriov *sriov;
|
|
|
+ int index;
|
|
|
+ u8 pci_func;
|
|
|
+
|
|
|
+ sriov = adapter->ahw->sriov;
|
|
|
+ pci_func = qlcnic_sriov_target_func_id(event);
|
|
|
+ index = qlcnic_sriov_func_to_index(adapter, pci_func);
|
|
|
+
|
|
|
+ if (index < 0)
|
|
|
+ return;
|
|
|
+
|
|
|
+ vf = &sriov->vf_info[index];
|
|
|
+ vf->pci_func = pci_func;
|
|
|
+
|
|
|
+ if (qlcnic_sriov_channel_free_check(event))
|
|
|
+ complete(&vf->ch_free_cmpl);
|
|
|
+
|
|
|
+ if (qlcnic_sriov_bc_msg_check(event))
|
|
|
+ qlcnic_sriov_handle_msg_event(sriov, vf);
|
|
|
+}
|
|
|
+
|
|
|
+int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable)
|
|
|
+{
|
|
|
+ struct qlcnic_cmd_args cmd;
|
|
|
+ int err;
|
|
|
+
|
|
|
+ if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP))
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ if (enable)
|
|
|
+ cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7);
|
|
|
+
|
|
|
+ err = qlcnic_83xx_mbx_op(adapter, &cmd);
|
|
|
+
|
|
|
+ if (err != QLCNIC_RCODE_SUCCESS) {
|
|
|
+ dev_err(&adapter->pdev->dev,
|
|
|
+ "Failed to %s bc events, err=%d\n",
|
|
|
+ (enable ? "enable" : "disable"), err);
|
|
|
+ }
|
|
|
+
|
|
|
+ qlcnic_free_mbx_args(&cmd);
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static int qlcnic_sriov_vf_mbx_op(struct qlcnic_adapter *adapter,
|
|
|
+ struct qlcnic_cmd_args *cmd)
|
|
|
+{
|
|
|
+ struct qlcnic_bc_trans *trans;
|
|
|
+ int err;
|
|
|
+ u32 rsp_data, opcode, mbx_err_code, rsp;
|
|
|
+ u16 seq = ++adapter->ahw->sriov->bc.trans_counter;
|
|
|
+
|
|
|
+ if (qlcnic_sriov_alloc_bc_trans(&trans))
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ if (qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND))
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
|
|
|
+ rsp = -EIO;
|
|
|
+ QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n",
|
|
|
+ QLCNIC_MBX_RSP(cmd->req.arg[0]), adapter->ahw->pci_func);
|
|
|
+ goto err_out;
|
|
|
+ }
|
|
|
+
|
|
|
+ err = qlcnic_sriov_send_bc_cmd(adapter, trans, adapter->ahw->pci_func);
|
|
|
+ if (err) {
|
|
|
+ dev_err(&adapter->pdev->dev,
|
|
|
+ "MBX command 0x%x timed out for VF %d\n",
|
|
|
+ (cmd->req.arg[0] & 0xffff), adapter->ahw->pci_func);
|
|
|
+ rsp = QLCNIC_RCODE_TIMEOUT;
|
|
|
+ goto err_out;
|
|
|
+ }
|
|
|
+
|
|
|
+ rsp_data = cmd->rsp.arg[0];
|
|
|
+ mbx_err_code = QLCNIC_MBX_STATUS(rsp_data);
|
|
|
+ opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]);
|
|
|
+
|
|
|
+ if ((mbx_err_code == QLCNIC_MBX_RSP_OK) ||
|
|
|
+ (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) {
|
|
|
+ rsp = QLCNIC_RCODE_SUCCESS;
|
|
|
+ } else {
|
|
|
+ rsp = mbx_err_code;
|
|
|
+ if (!rsp)
|
|
|
+ rsp = 1;
|
|
|
+ dev_err(&adapter->pdev->dev,
|
|
|
+ "MBX command 0x%x failed with err:0x%x for VF %d\n",
|
|
|
+ opcode, mbx_err_code, adapter->ahw->pci_func);
|
|
|
+ }
|
|
|
+
|
|
|
+err_out:
|
|
|
+ qlcnic_sriov_cleanup_transaction(trans);
|
|
|
+ return rsp;
|
|
|
+}
|
|
|
+
|
|
|
+int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op)
|
|
|
+{
|
|
|
+ struct qlcnic_cmd_args cmd;
|
|
|
+ struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0];
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op))
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ ret = qlcnic_issue_cmd(adapter, &cmd);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&adapter->pdev->dev,
|
|
|
+ "Failed bc channel %s %d\n", cmd_op ? "term" : "init",
|
|
|
+ ret);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ cmd_op = (cmd.rsp.arg[0] & 0xff);
|
|
|
+ if (cmd.rsp.arg[0] >> 25 == 2)
|
|
|
+ return 2;
|
|
|
+ if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT)
|
|
|
+ set_bit(QLC_BC_VF_STATE, &vf->state);
|
|
|
+ else
|
|
|
+ clear_bit(QLC_BC_VF_STATE, &vf->state);
|
|
|
+
|
|
|
+out:
|
|
|
+ qlcnic_free_mbx_args(&cmd);
|
|
|
+ return ret;
|
|
|
+}
|
Rajesh Borundia