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@@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- return intel_crtc->cpu_transcoder;
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+ return intel_crtc->config.cpu_transcoder;
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}
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static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
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@@ -1227,8 +1227,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
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if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
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state = true;
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- if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
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- !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
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+ if (!intel_using_power_well(dev_priv->dev) &&
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+ cpu_transcoder != TRANSCODER_EDP) {
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cur_state = false;
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} else {
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reg = PIPECONF(cpu_transcoder);
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@@ -2002,8 +2002,10 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
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alignment = 0;
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break;
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case I915_TILING_Y:
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- /* FIXME: Is this true? */
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- DRM_ERROR("Y tiled not allowed for scan out buffers\n");
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+ /* Despite that we check this in framebuffer_init userspace can
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+ * screw us over and change the tiling after the fact. Only
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+ * pinned buffers can't change their tiling. */
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+ DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
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return -EINVAL;
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default:
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BUG();
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@@ -3201,7 +3203,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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+ enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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assert_transcoder_disabled(dev_priv, TRANSCODER_A);
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@@ -3576,7 +3578,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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+ enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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if (!intel_crtc->active)
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return;
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@@ -3597,9 +3599,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
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- /* Disable PF */
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- I915_WRITE(PF_CTL(pipe), 0);
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- I915_WRITE(PF_WIN_SZ(pipe), 0);
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+ /* XXX: Once we have proper panel fitter state tracking implemented with
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+ * hardware state read/check support we should switch to only disable
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+ * the panel fitter when we know it's used. */
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+ if (intel_using_power_well(dev)) {
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+ I915_WRITE(PF_CTL(pipe), 0);
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+ I915_WRITE(PF_WIN_SZ(pipe), 0);
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+ }
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intel_ddi_disable_pipe_clock(intel_crtc);
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@@ -3632,7 +3638,7 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
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/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
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* start using it. */
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- intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
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+ intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
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intel_ddi_put_crtc_pll(crtc);
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}
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@@ -3718,6 +3724,26 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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encoder->enable(encoder);
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}
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+static void i9xx_pfit_disable(struct intel_crtc *crtc)
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+{
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+ struct drm_device *dev = crtc->base.dev;
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ enum pipe pipe;
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+ uint32_t pctl = I915_READ(PFIT_CONTROL);
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+
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+ assert_pipe_disabled(dev_priv, crtc->pipe);
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+
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+ if (INTEL_INFO(dev)->gen >= 4)
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+ pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
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+ else
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+ pipe = PIPE_B;
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+
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+ if (pipe == crtc->pipe) {
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+ DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
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+ I915_WRITE(PFIT_CONTROL, 0);
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+ }
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+}
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+
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static void i9xx_crtc_disable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@@ -3726,8 +3752,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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- u32 pctl;
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-
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if (!intel_crtc->active)
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return;
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@@ -3747,11 +3771,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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intel_disable_plane(dev_priv, plane, pipe);
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intel_disable_pipe(dev_priv, pipe);
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- /* Disable pannel fitter if it is on this pipe. */
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- pctl = I915_READ(PFIT_CONTROL);
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- if ((pctl & PFIT_ENABLE) &&
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- ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
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- I915_WRITE(PFIT_CONTROL, 0);
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+ i9xx_pfit_disable(intel_crtc);
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intel_disable_pll(dev_priv, pipe);
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@@ -3983,9 +4003,9 @@ static bool intel_crtc_compute_config(struct drm_crtc *crtc,
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adjusted_mode->hsync_start == adjusted_mode->hdisplay)
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return false;
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- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
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+ if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
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pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
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- } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
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+ } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
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/* only a 8bpc pipe, with 6bpc dither through the panel fitter
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* for lvds. */
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pipe_config->pipe_bpp = 8*3;
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@@ -4474,7 +4494,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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+ enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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uint32_t vsyncshift;
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if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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@@ -4956,13 +4976,6 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
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tmp |= (0x12 << 24);
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intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
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- if (!is_sdv) {
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- tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
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- tmp &= ~(0x3 << 6);
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- tmp |= (1 << 6) | (1 << 0);
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- intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
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- }
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-
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if (is_sdv) {
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tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
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tmp |= 0x7FFF;
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@@ -5223,7 +5236,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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+ enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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uint32_t val;
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val = I915_READ(PIPECONF(cpu_transcoder));
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@@ -5417,7 +5430,7 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = crtc->pipe;
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- enum transcoder transcoder = crtc->cpu_transcoder;
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+ enum transcoder transcoder = crtc->config.cpu_transcoder;
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if (INTEL_INFO(dev)->gen >= 5) {
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I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
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@@ -5469,7 +5482,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
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}
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static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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- intel_clock_t *clock, u32 fp)
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+ intel_clock_t *clock, u32 *fp,
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+ intel_clock_t *reduced_clock, u32 *fp2)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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@@ -5503,13 +5517,16 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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if (is_lvds) {
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if ((intel_panel_use_ssc(dev_priv) &&
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dev_priv->lvds_ssc_freq == 100) ||
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- intel_is_dual_link_lvds(dev))
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+ (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
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factor = 25;
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} else if (is_sdvo && is_tv)
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factor = 20;
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if (clock->m < factor * clock->n)
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- fp |= FP_CB_TUNE;
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+ *fp |= FP_CB_TUNE;
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+
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+ if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
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+ *fp2 |= FP_CB_TUNE;
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dpll = 0;
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@@ -5596,7 +5613,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
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"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
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- intel_crtc->cpu_transcoder = pipe;
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+ intel_crtc->config.cpu_transcoder = pipe;
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock, &reduced_clock);
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@@ -5626,7 +5643,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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- dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
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+ dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
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+ has_reduced_clock ? &fp2 : NULL);
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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@@ -5779,9 +5797,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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}
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if (is_cpu_edp)
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- intel_crtc->cpu_transcoder = TRANSCODER_EDP;
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+ intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
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else
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- intel_crtc->cpu_transcoder = pipe;
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+ intel_crtc->config.cpu_transcoder = pipe;
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/* We are not sure yet this won't happen. */
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WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
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@@ -5790,7 +5808,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
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num_connectors, pipe_name(pipe));
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- WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
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+ WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
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(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
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WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
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@@ -5841,7 +5859,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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- tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
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+ tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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@@ -6809,7 +6827,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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+ enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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struct drm_display_mode *mode;
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int htot = I915_READ(HTOTAL(cpu_transcoder));
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int hsync = I915_READ(HSYNC(cpu_transcoder));
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@@ -7708,22 +7726,25 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
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if (crtc->enabled)
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*prepare_pipes |= 1 << intel_crtc->pipe;
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- /* We only support modeset on one single crtc, hence we need to do that
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- * only for the passed in crtc iff we change anything else than just
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- * disable crtcs.
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- *
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- * This is actually not true, to be fully compatible with the old crtc
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- * helper we automatically disable _any_ output (i.e. doesn't need to be
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- * connected to the crtc we're modesetting on) if it's disconnected.
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- * Which is a rather nutty api (since changed the output configuration
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- * without userspace's explicit request can lead to confusion), but
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- * alas. Hence we currently need to modeset on all pipes we prepare. */
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+ /*
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+ * For simplicity do a full modeset on any pipe where the output routing
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+ * changed. We could be more clever, but that would require us to be
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+ * more careful with calling the relevant encoder->mode_set functions.
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+ */
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if (*prepare_pipes)
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*modeset_pipes = *prepare_pipes;
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/* ... and mask these out. */
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*modeset_pipes &= ~(*disable_pipes);
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*prepare_pipes &= ~(*disable_pipes);
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+
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+ /*
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+ * HACK: We don't (yet) fully support global modesets. intel_set_config
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+ * obies this rule, but the modeset restore mode of
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+ * intel_modeset_setup_hw_state does not.
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+ */
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+ *modeset_pipes &= 1 << intel_crtc->pipe;
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+ *prepare_pipes &= 1 << intel_crtc->pipe;
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}
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|
|
static bool intel_crtc_in_use(struct drm_crtc *crtc)
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@@ -7916,9 +7937,9 @@ intel_modeset_check_state(struct drm_device *dev)
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}
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}
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|
|
-int intel_set_mode(struct drm_crtc *crtc,
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- struct drm_display_mode *mode,
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- int x, int y, struct drm_framebuffer *fb)
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+static int __intel_set_mode(struct drm_crtc *crtc,
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+ struct drm_display_mode *mode,
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+ int x, int y, struct drm_framebuffer *fb)
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{
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struct drm_device *dev = crtc->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
|
|
@@ -7969,10 +7990,12 @@ int intel_set_mode(struct drm_crtc *crtc,
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* to set it here already despite that we pass it down the callchain.
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*/
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if (modeset_pipes) {
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+ enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
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crtc->mode = *mode;
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|
|
/* mode_set/enable/disable functions rely on a correct pipe
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* config. */
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|
to_intel_crtc(crtc)->config = *pipe_config;
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+ to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
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}
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|
|
|
|
|
/* Only after disabling all output pipelines that will be changed can we
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|
@@ -8012,8 +8035,6 @@ done:
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|
|
if (ret && crtc->enabled) {
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|
|
crtc->hwmode = *saved_hwmode;
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|
crtc->mode = *saved_mode;
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|
|
- } else {
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|
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- intel_modeset_check_state(dev);
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}
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out:
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|
@@ -8022,6 +8043,20 @@ out:
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return ret;
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|
}
|
|
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|
|
+int intel_set_mode(struct drm_crtc *crtc,
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|
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+ struct drm_display_mode *mode,
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|
+ int x, int y, struct drm_framebuffer *fb)
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|
+{
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+ int ret;
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+
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+ ret = __intel_set_mode(crtc, mode, x, y, fb);
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+
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+ if (ret == 0)
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+ intel_modeset_check_state(crtc->dev);
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+
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+ return ret;
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+}
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+
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void intel_crtc_restore_mode(struct drm_crtc *crtc)
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{
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intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
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@@ -8371,7 +8406,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
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/* Swap pipes & planes for FBC on pre-965 */
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intel_crtc->pipe = pipe;
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|
intel_crtc->plane = pipe;
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- intel_crtc->cpu_transcoder = pipe;
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+ intel_crtc->config.cpu_transcoder = pipe;
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if (IS_MOBILE(dev) && IS_GEN3(dev)) {
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|
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
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|
intel_crtc->plane = !pipe;
|
|
@@ -8462,7 +8497,7 @@ static void intel_setup_outputs(struct drm_device *dev)
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|
I915_WRITE(PFIT_CONTROL, 0);
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|
|
}
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|
|
|
|
|
- if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
|
|
|
+ if (!IS_ULT(dev))
|
|
|
intel_crt_init(dev);
|
|
|
|
|
|
if (HAS_DDI(dev)) {
|
|
@@ -8991,6 +9026,9 @@ void intel_modeset_init(struct drm_device *dev)
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|
|
|
|
|
intel_init_pm(dev);
|
|
|
|
|
|
+ if (INTEL_INFO(dev)->num_pipes == 0)
|
|
|
+ return;
|
|
|
+
|
|
|
intel_init_display(dev);
|
|
|
|
|
|
if (IS_GEN2(dev)) {
|
|
@@ -9093,7 +9131,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
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|
|
u32 reg;
|
|
|
|
|
|
/* Clear any frame start delays used for debugging left by the BIOS */
|
|
|
- reg = PIPECONF(crtc->cpu_transcoder);
|
|
|
+ reg = PIPECONF(crtc->config.cpu_transcoder);
|
|
|
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
|
|
|
|
|
|
/* We need to sanitize the plane -> pipe mapping first because this will
|
|
@@ -9259,7 +9297,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
|
|
|
}
|
|
|
|
|
|
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
- crtc->cpu_transcoder = TRANSCODER_EDP;
|
|
|
+ crtc->config.cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
|
|
DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
|
|
|
pipe_name(pipe));
|
|
@@ -9269,7 +9307,10 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
|
|
|
setup_pipes:
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list,
|
|
|
base.head) {
|
|
|
+ enum transcoder tmp = crtc->config.cpu_transcoder;
|
|
|
memset(&crtc->config, 0, sizeof(crtc->config));
|
|
|
+ crtc->config.cpu_transcoder = tmp;
|
|
|
+
|
|
|
crtc->active = dev_priv->display.get_pipe_config(crtc,
|
|
|
&crtc->config);
|
|
|
|
|
@@ -9330,10 +9371,16 @@ setup_pipes:
|
|
|
}
|
|
|
|
|
|
if (force_restore) {
|
|
|
+ /*
|
|
|
+ * We need to use raw interfaces for restoring state to avoid
|
|
|
+ * checking (bogus) intermediate states.
|
|
|
+ */
|
|
|
for_each_pipe(pipe) {
|
|
|
struct drm_crtc *crtc =
|
|
|
dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
- intel_crtc_restore_mode(crtc);
|
|
|
+
|
|
|
+ __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
|
|
|
+ crtc->fb);
|
|
|
}
|
|
|
list_for_each_entry(plane, &dev->mode_config.plane_list, head)
|
|
|
intel_plane_restore(plane);
|
|
@@ -9398,6 +9445,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
|
|
/* flush any delayed tasks or pending work */
|
|
|
flush_scheduled_work();
|
|
|
|
|
|
+ /* destroy backlight, if any, before the connectors */
|
|
|
+ intel_panel_destroy_backlight(dev);
|
|
|
+
|
|
|
drm_mode_config_cleanup(dev);
|
|
|
|
|
|
intel_cleanup_overlay(dev);
|