|
|
@@ -39,6 +39,7 @@
|
|
|
#include "iwl-rfkill.h"
|
|
|
#include "iwl-power.h"
|
|
|
#include "iwl-sta.h"
|
|
|
+#include "iwl-helpers.h"
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("iwl core");
|
|
|
@@ -59,6 +60,8 @@ MODULE_LICENSE("GPL");
|
|
|
IWL_RATE_##pp##M_INDEX, \
|
|
|
IWL_RATE_##np##M_INDEX }
|
|
|
|
|
|
+static irqreturn_t iwl_isr(int irq, void *data);
|
|
|
+
|
|
|
/*
|
|
|
* Parameter order:
|
|
|
* rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
|
|
|
@@ -1501,7 +1504,266 @@ void iwl_enable_interrupts(struct iwl_priv *priv)
|
|
|
}
|
|
|
EXPORT_SYMBOL(iwl_enable_interrupts);
|
|
|
|
|
|
-irqreturn_t iwl_isr(int irq, void *data)
|
|
|
+
|
|
|
+#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
|
|
|
+
|
|
|
+/* Free dram table */
|
|
|
+void iwl_free_isr_ict(struct iwl_priv *priv)
|
|
|
+{
|
|
|
+ if (priv->ict_tbl_vir) {
|
|
|
+ pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
|
|
|
+ PAGE_SIZE, priv->ict_tbl_vir,
|
|
|
+ priv->ict_tbl_dma);
|
|
|
+ priv->ict_tbl_vir = NULL;
|
|
|
+ }
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iwl_free_isr_ict);
|
|
|
+
|
|
|
+
|
|
|
+/* allocate dram shared table it is a PAGE_SIZE aligned
|
|
|
+ * also reset all data related to ICT table interrupt.
|
|
|
+ */
|
|
|
+int iwl_alloc_isr_ict(struct iwl_priv *priv)
|
|
|
+{
|
|
|
+
|
|
|
+ if (priv->cfg->use_isr_legacy)
|
|
|
+ return 0;
|
|
|
+ /* allocate shrared data table */
|
|
|
+ priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
|
|
|
+ ICT_COUNT) + PAGE_SIZE,
|
|
|
+ &priv->ict_tbl_dma);
|
|
|
+ if (!priv->ict_tbl_vir)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ /* align table to PAGE_SIZE boundry */
|
|
|
+ priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
|
|
|
+
|
|
|
+ IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
|
|
|
+ (unsigned long long)priv->ict_tbl_dma,
|
|
|
+ (unsigned long long)priv->aligned_ict_tbl_dma,
|
|
|
+ (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
|
|
|
+
|
|
|
+ priv->ict_tbl = priv->ict_tbl_vir +
|
|
|
+ (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
|
|
|
+
|
|
|
+ IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
|
|
|
+ priv->ict_tbl, priv->ict_tbl_vir,
|
|
|
+ (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
|
|
|
+
|
|
|
+ /* reset table and index to all 0 */
|
|
|
+ memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
|
|
|
+ priv->ict_index = 0;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iwl_alloc_isr_ict);
|
|
|
+
|
|
|
+/* Device is going up inform it about using ICT interrupt table,
|
|
|
+ * also we need to tell the driver to start using ICT interrupt.
|
|
|
+ */
|
|
|
+int iwl_reset_ict(struct iwl_priv *priv)
|
|
|
+{
|
|
|
+ u32 val;
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ if (!priv->ict_tbl_vir)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
|
+ iwl_disable_interrupts(priv);
|
|
|
+
|
|
|
+ memset(&priv->ict_tbl[0],0, sizeof(u32) * ICT_COUNT);
|
|
|
+
|
|
|
+ val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
|
|
|
+
|
|
|
+ val |= CSR_DRAM_INT_TBL_ENABLE;
|
|
|
+ val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
|
|
|
+
|
|
|
+ IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
|
|
|
+ "aligned dma address %Lx\n",
|
|
|
+ val, (unsigned long long)priv->aligned_ict_tbl_dma);
|
|
|
+
|
|
|
+ iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
|
|
|
+ priv->use_ict = true;
|
|
|
+ priv->ict_index = 0;
|
|
|
+ iwl_write32(priv, CSR_INT, CSR_INI_SET_MASK);
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iwl_reset_ict);
|
|
|
+
|
|
|
+/* Device is going down disable ict interrupt usage */
|
|
|
+void iwl_disable_ict(struct iwl_priv *priv)
|
|
|
+{
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
|
+ priv->use_ict = false;
|
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iwl_disable_ict);
|
|
|
+
|
|
|
+/* interrupt handler using ict table, with this interrupt driver will
|
|
|
+ * stop using INTA register to get device's interrupt, reading this register
|
|
|
+ * is expensive, device will write interrupts in ICT dram table, increment
|
|
|
+ * index then will fire interrupt to driver, driver will OR all ICT table
|
|
|
+ * entries from current index up to table entry with 0 value. the result is
|
|
|
+ * the interrupt we need to service, driver will set the entries back to 0 and
|
|
|
+ * set index.
|
|
|
+ */
|
|
|
+irqreturn_t iwl_isr_ict(int irq, void *data)
|
|
|
+{
|
|
|
+ struct iwl_priv *priv = data;
|
|
|
+ u32 inta, inta_mask;
|
|
|
+ u32 val = 0;
|
|
|
+
|
|
|
+ if (!priv)
|
|
|
+ return IRQ_NONE;
|
|
|
+
|
|
|
+ /* dram interrupt table not set yet,
|
|
|
+ * use legacy interrupt.
|
|
|
+ */
|
|
|
+ if (!priv->use_ict)
|
|
|
+ return iwl_isr(irq, data);
|
|
|
+
|
|
|
+ spin_lock(&priv->lock);
|
|
|
+
|
|
|
+ /* Disable (but don't clear!) interrupts here to avoid
|
|
|
+ * back-to-back ISRs and sporadic interrupts from our NIC.
|
|
|
+ * If we have something to service, the tasklet will re-enable ints.
|
|
|
+ * If we *don't* have something, we'll re-enable before leaving here.
|
|
|
+ */
|
|
|
+ inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
|
|
|
+ iwl_write32(priv, CSR_INT_MASK, 0x00000000);
|
|
|
+
|
|
|
+
|
|
|
+ /* Ignore interrupt if there's nothing in NIC to service.
|
|
|
+ * This may be due to IRQ shared with another device,
|
|
|
+ * or due to sporadic interrupts thrown from our NIC. */
|
|
|
+ if (!priv->ict_tbl[priv->ict_index]) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
|
|
|
+ goto none;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* read all entries that not 0 start with ict_index */
|
|
|
+ while (priv->ict_tbl[priv->ict_index]) {
|
|
|
+
|
|
|
+ val |= priv->ict_tbl[priv->ict_index];
|
|
|
+ IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
|
|
|
+ priv->ict_index,
|
|
|
+ priv->ict_tbl[priv->ict_index]);
|
|
|
+ priv->ict_tbl[priv->ict_index] = 0;
|
|
|
+ priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
|
|
|
+ ICT_COUNT);
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+ /* We should not get this value, just ignore it. */
|
|
|
+ if (val == 0xffffffff)
|
|
|
+ val = 0;
|
|
|
+
|
|
|
+ inta = (0xff & val) | ((0xff00 & val) << 16);
|
|
|
+ IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
|
|
|
+ inta, inta_mask, val);
|
|
|
+
|
|
|
+ inta &= CSR_INI_SET_MASK;
|
|
|
+ priv->inta |= inta;
|
|
|
+
|
|
|
+ /* iwl_irq_tasklet() will service interrupts and re-enable them */
|
|
|
+ if (likely(inta))
|
|
|
+ tasklet_schedule(&priv->irq_tasklet);
|
|
|
+ else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
|
|
|
+ /* Allow interrupt if was disabled by this handler and
|
|
|
+ * no tasklet was schedules, We should not enable interrupt,
|
|
|
+ * tasklet will enable it.
|
|
|
+ */
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_unlock(&priv->lock);
|
|
|
+ return IRQ_HANDLED;
|
|
|
+
|
|
|
+ none:
|
|
|
+ /* re-enable interrupts here since we don't have anything to service.
|
|
|
+ * only Re-enable if disabled by irq.
|
|
|
+ */
|
|
|
+ if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+
|
|
|
+ spin_unlock(&priv->lock);
|
|
|
+ return IRQ_NONE;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL(iwl_isr_ict);
|
|
|
+
|
|
|
+
|
|
|
+static irqreturn_t iwl_isr(int irq, void *data)
|
|
|
+{
|
|
|
+ struct iwl_priv *priv = data;
|
|
|
+ u32 inta, inta_mask;
|
|
|
+ u32 inta_fh;
|
|
|
+
|
|
|
+ if (!priv)
|
|
|
+ return IRQ_NONE;
|
|
|
+
|
|
|
+ spin_lock(&priv->lock);
|
|
|
+
|
|
|
+ /* Disable (but don't clear!) interrupts here to avoid
|
|
|
+ * back-to-back ISRs and sporadic interrupts from our NIC.
|
|
|
+ * If we have something to service, the tasklet will re-enable ints.
|
|
|
+ * If we *don't* have something, we'll re-enable before leaving here. */
|
|
|
+ inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
|
|
|
+ iwl_write32(priv, CSR_INT_MASK, 0x00000000);
|
|
|
+
|
|
|
+ /* Discover which interrupts are active/pending */
|
|
|
+ inta = iwl_read32(priv, CSR_INT);
|
|
|
+
|
|
|
+ /* Ignore interrupt if there's nothing in NIC to service.
|
|
|
+ * This may be due to IRQ shared with another device,
|
|
|
+ * or due to sporadic interrupts thrown from our NIC. */
|
|
|
+ if (!inta) {
|
|
|
+ IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
|
|
|
+ goto none;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
|
|
|
+ /* Hardware disappeared. It might have already raised
|
|
|
+ * an interrupt */
|
|
|
+ IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
|
|
|
+ goto unplugged;
|
|
|
+ }
|
|
|
+
|
|
|
+#ifdef CONFIG_IWLWIFI_DEBUG
|
|
|
+ if (priv->debug_level & (IWL_DL_ISR)) {
|
|
|
+ inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
|
|
|
+ IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
|
|
|
+ "fh 0x%08x\n", inta, inta_mask, inta_fh);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ priv->inta |= inta;
|
|
|
+ /* iwl_irq_tasklet() will service interrupts and re-enable them */
|
|
|
+ if (likely(inta))
|
|
|
+ tasklet_schedule(&priv->irq_tasklet);
|
|
|
+ else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+
|
|
|
+ unplugged:
|
|
|
+ spin_unlock(&priv->lock);
|
|
|
+ return IRQ_HANDLED;
|
|
|
+
|
|
|
+ none:
|
|
|
+ /* re-enable interrupts here since we don't have anything to service. */
|
|
|
+ /* only Re-enable if diabled by irq and no schedules tasklet. */
|
|
|
+ if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
|
|
|
+ iwl_enable_interrupts(priv);
|
|
|
+
|
|
|
+ spin_unlock(&priv->lock);
|
|
|
+ return IRQ_NONE;
|
|
|
+}
|
|
|
+
|
|
|
+irqreturn_t iwl_isr_legacy(int irq, void *data)
|
|
|
{
|
|
|
struct iwl_priv *priv = data;
|
|
|
u32 inta, inta_mask;
|
|
|
@@ -1558,7 +1820,7 @@ irqreturn_t iwl_isr(int irq, void *data)
|
|
|
spin_unlock(&priv->lock);
|
|
|
return IRQ_NONE;
|
|
|
}
|
|
|
-EXPORT_SYMBOL(iwl_isr);
|
|
|
+EXPORT_SYMBOL(iwl_isr_legacy);
|
|
|
|
|
|
int iwl_send_bt_config(struct iwl_priv *priv)
|
|
|
{
|
Mohamed Abbas