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@@ -6018,10 +6018,11 @@ void bnx2x_nic_init_cnic(struct bnx2x *bp)
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mmiowb();
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}
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-void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
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+void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
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{
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int i;
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+ /* Setup NIC internals and enable interrupts */
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for_each_eth_queue(bp, i)
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bnx2x_init_eth_fp(bp, i);
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@@ -6030,17 +6031,21 @@ void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
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bnx2x_init_rx_rings(bp);
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bnx2x_init_tx_rings(bp);
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- if (IS_VF(bp))
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- return;
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+ if (IS_PF(bp)) {
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+ /* Initialize MOD_ABS interrupts */
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+ bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
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+ bp->common.shmem_base,
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+ bp->common.shmem2_base, BP_PORT(bp));
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- /* Initialize MOD_ABS interrupts */
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- bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
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- bp->common.shmem_base, bp->common.shmem2_base,
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- BP_PORT(bp));
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+ /* initialize the default status block and sp ring */
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+ bnx2x_init_def_sb(bp);
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+ bnx2x_update_dsb_idx(bp);
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+ bnx2x_init_sp_ring(bp);
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+ }
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+}
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- bnx2x_init_def_sb(bp);
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- bnx2x_update_dsb_idx(bp);
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- bnx2x_init_sp_ring(bp);
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+void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
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+{
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bnx2x_init_eq_ring(bp);
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bnx2x_init_internal(bp, load_code);
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bnx2x_pf_init(bp);
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@@ -6058,12 +6063,7 @@ void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
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AEU_INPUTS_ATTN_BITS_SPIO5);
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}
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-/* end of nic init */
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-
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-/*
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- * gzip service functions
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- */
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-
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+/* gzip service functions */
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static int bnx2x_gunzip_init(struct bnx2x *bp)
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{
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bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
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