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@@ -256,6 +256,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
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pci_save_state(dev->pdev);
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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+ /* Display arbitration control */
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+ dev_priv->saveDSPARB = I915_READ(DSPARB);
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+
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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@@ -349,6 +352,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
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dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
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/* Clock gating state */
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+ dev_priv->saveD_STATE = I915_READ(D_STATE);
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dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
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/* Cache mode state */
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@@ -388,6 +392,8 @@ static int i915_resume(struct drm_device *dev)
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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+ I915_WRITE(DSPARB, dev_priv->saveDSPARB);
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+
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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@@ -507,6 +513,7 @@ static int i915_resume(struct drm_device *dev)
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udelay(150);
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/* Clock gating state */
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+ I915_WRITE (D_STATE, dev_priv->saveD_STATE);
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I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
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/* Cache mode state */
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