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@@ -3731,6 +3731,28 @@ static void tg3_nvram_unlock(struct tg3 *tp)
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tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
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}
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+/* tp->lock is held. */
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+static void tg3_enable_nvram_access(struct tg3 *tp)
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+{
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+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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+ u32 nvaccess = tr32(NVRAM_ACCESS);
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+
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+ tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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+ }
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+}
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+
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+/* tp->lock is held. */
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+static void tg3_disable_nvram_access(struct tg3 *tp)
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+{
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+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
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+ u32 nvaccess = tr32(NVRAM_ACCESS);
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+
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+ tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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+ }
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+}
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+
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/* tp->lock is held. */
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static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
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{
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@@ -7102,6 +7124,10 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
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nvcfg1 = tr32(NVRAM_CFG1);
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+ /* NVRAM protection for TPM */
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+ if (nvcfg1 & (1 << 27))
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+ tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
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+
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switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
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case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
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case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
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@@ -7179,11 +7205,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
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tp->tg3_flags |= TG3_FLAG_NVRAM;
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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- }
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+ tg3_enable_nvram_access(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tg3_get_5752_nvram_info(tp);
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@@ -7192,11 +7214,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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tg3_get_nvram_size(tp);
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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- }
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+ tg3_disable_nvram_access(tp);
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} else {
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tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
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@@ -7285,11 +7303,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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tg3_nvram_lock(tp);
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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- }
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+ tg3_enable_nvram_access(tp);
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tw32(NVRAM_ADDR, offset);
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ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
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@@ -7300,11 +7314,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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tg3_nvram_unlock(tp);
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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- }
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+ tg3_disable_nvram_access(tp);
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return ret;
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}
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@@ -7367,7 +7377,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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while (len) {
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int j;
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- u32 phy_addr, page_off, size, nvaccess;
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+ u32 phy_addr, page_off, size;
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phy_addr = offset & ~pagemask;
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@@ -7390,8 +7400,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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offset = offset + (pagesize - page_off);
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- nvaccess = tr32(NVRAM_ACCESS);
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- tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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+ tg3_enable_nvram_access(tp);
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/*
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* Before we can erase the flash page, we need
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@@ -7528,13 +7537,10 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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tg3_nvram_lock(tp);
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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-
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+ tg3_enable_nvram_access(tp);
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+ if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
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+ !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
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tw32(NVRAM_WRITE1, 0x406);
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- }
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grc_mode = tr32(GRC_MODE);
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tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
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@@ -7553,11 +7559,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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grc_mode = tr32(GRC_MODE);
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tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
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- if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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- u32 nvaccess = tr32(NVRAM_ACCESS);
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-
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- tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
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- }
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+ tg3_disable_nvram_access(tp);
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tg3_nvram_unlock(tp);
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}
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