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@@ -643,95 +643,18 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
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!!erp->short_preamble);
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rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
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-}
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-
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-
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-static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
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- struct rt2x00lib_conf *libconf)
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-{
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- u16 eeprom;
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- short lna_gain = 0;
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-
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- if (libconf->band == IEEE80211_BAND_2GHZ) {
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- if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
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- lna_gain += 14;
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-
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- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
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- lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
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- } else {
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- if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
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- lna_gain += 14;
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-
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- rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
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- lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
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- }
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-
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- rt2x00dev->lna_gain = lna_gain;
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-}
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-
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-static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
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- const int basic_rate_mask)
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-{
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- rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
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-}
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-
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-static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
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- struct rf_channel *rf, const int txpower)
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-{
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- u8 r3;
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- u8 r94;
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- u8 smart;
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-
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- rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
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- rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
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-
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- smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
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- rt2x00_rf(&rt2x00dev->chip, RF2527));
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-
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- rt61pci_bbp_read(rt2x00dev, 3, &r3);
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- rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
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- rt61pci_bbp_write(rt2x00dev, 3, r3);
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-
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- r94 = 6;
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- if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
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- r94 += txpower - MAX_TXPOWER;
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- else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
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- r94 += txpower;
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- rt61pci_bbp_write(rt2x00dev, 94, r94);
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-
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- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
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- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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-
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- udelay(200);
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-
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- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
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- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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-
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- udelay(200);
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-
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- rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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- rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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- rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
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- rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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-
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- msleep(1);
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-}
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-static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
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- const int txpower)
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-{
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- struct rf_channel rf;
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
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- rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
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- rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
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- rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
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- rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
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+ rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
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+ rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
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+ rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
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- rt61pci_config_channel(rt2x00dev, &rf, txpower);
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+ rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
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+ rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
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+ rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
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+ rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
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+ rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
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}
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static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
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@@ -906,8 +829,8 @@ static const struct antenna_sel antenna_sel_bg[] = {
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{ 98, { 0x48, 0x48 } },
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};
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-static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
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- struct antenna_setup *ant)
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+static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
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+ struct antenna_setup *ant)
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{
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const struct antenna_sel *sel;
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unsigned int lna;
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@@ -954,20 +877,105 @@ static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
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}
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}
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-static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
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+static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
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+ struct rt2x00lib_conf *libconf)
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+{
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+ u16 eeprom;
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+ short lna_gain = 0;
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+
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+ if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
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+ if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
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+ lna_gain += 14;
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+
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+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
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+ lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
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+ } else {
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+ if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
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+ lna_gain += 14;
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+
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+ rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
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+ lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
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+ }
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+
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+ rt2x00dev->lna_gain = lna_gain;
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+}
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+
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+static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
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+ struct rf_channel *rf, const int txpower)
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+{
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+ u8 r3;
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+ u8 r94;
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+ u8 smart;
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+
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+ rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
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+ rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
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+
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+ smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
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+ rt2x00_rf(&rt2x00dev->chip, RF2527));
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+
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+ rt61pci_bbp_read(rt2x00dev, 3, &r3);
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+ rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
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+ rt61pci_bbp_write(rt2x00dev, 3, r3);
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+
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+ r94 = 6;
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+ if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
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+ r94 += txpower - MAX_TXPOWER;
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+ else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
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+ r94 += txpower;
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+ rt61pci_bbp_write(rt2x00dev, 94, r94);
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+
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+ rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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+ rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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+ rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
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+ rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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+
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+ udelay(200);
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+
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+ rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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+ rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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+ rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
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+ rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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+
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+ udelay(200);
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+
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+ rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
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+ rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
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+ rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
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+ rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
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+
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+ msleep(1);
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+}
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+
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+static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
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+ const int txpower)
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+{
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+ struct rf_channel rf;
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+
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+ rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
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+ rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
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+ rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
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+ rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
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+
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+ rt61pci_config_channel(rt2x00dev, &rf, txpower);
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+}
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+
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+static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
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struct rt2x00lib_conf *libconf)
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{
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u32 reg;
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- rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
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- rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
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- rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
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+ rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
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+ rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
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+ libconf->conf->long_frame_max_tx_count);
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+ rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
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+ libconf->conf->short_frame_max_tx_count);
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+ rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
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+}
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- rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
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- rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
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- rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
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- rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
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- rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
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+static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
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+ struct rt2x00lib_conf *libconf)
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+{
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+ u32 reg;
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rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
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rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
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@@ -990,16 +998,15 @@ static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
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/* Always recalculate LNA gain before changing configuration */
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rt61pci_config_lna_gain(rt2x00dev, libconf);
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- if (flags & CONFIG_UPDATE_PHYMODE)
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- rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
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- if (flags & CONFIG_UPDATE_CHANNEL)
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+ if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
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rt61pci_config_channel(rt2x00dev, &libconf->rf,
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libconf->conf->power_level);
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- if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
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+ if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
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+ !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
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rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
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- if (flags & CONFIG_UPDATE_ANTENNA)
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- rt61pci_config_antenna(rt2x00dev, &libconf->ant);
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- if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
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+ if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
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+ rt61pci_config_retry_limit(rt2x00dev, libconf);
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+ if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
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rt61pci_config_duration(rt2x00dev, libconf);
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}
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@@ -2628,20 +2635,6 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
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/*
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* IEEE80211 stack callback functions.
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*/
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-static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
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- u32 short_retry, u32 long_retry)
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-{
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- struct rt2x00_dev *rt2x00dev = hw->priv;
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- u32 reg;
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-
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- rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
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- rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
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- rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
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- rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
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-
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- return 0;
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-}
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-
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static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
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const struct ieee80211_tx_queue_params *params)
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{
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@@ -2755,8 +2748,8 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
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.config_filter = rt61pci_config_filter,
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.config_intf = rt61pci_config_intf,
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.config_erp = rt61pci_config_erp,
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+ .config_ant = rt61pci_config_ant,
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.config = rt61pci_config,
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- .set_retry_limit = rt61pci_set_retry_limit,
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};
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static const struct data_queue_desc rt61pci_queue_rx = {
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