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@@ -17,7 +17,7 @@
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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-#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
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+#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
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#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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@@ -34,6 +34,5 @@
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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-#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
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#endif
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#endif
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