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@@ -109,6 +109,16 @@
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#define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
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#define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
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+#define EVENT_VALID_MASK \
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+ ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
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+ (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
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+ (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
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+ (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
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+ (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
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+ (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
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+ (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
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+ EVENT_PSEL_MASK)
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+
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/* MMCRA IFM bits - POWER8 */
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#define POWER8_MMCRA_IFM1 0x0000000040000000UL
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#define POWER8_MMCRA_IFM2 0x0000000080000000UL
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@@ -212,6 +222,9 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
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mask = value = 0;
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+ if (event & ~EVENT_VALID_MASK)
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+ return -1;
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+
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pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
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