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@@ -79,7 +79,6 @@ const char pch_driver_version[] = DRV_VERSION;
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#define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
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#define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
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-#define PCH_GBE_ETH_ALEN 6
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/* This defines the bits that are set in the Interrupt Mask
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* Set/Read Register. Each bit is documented below:
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@@ -519,7 +518,7 @@ static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
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if (mc_addr_count) {
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pch_gbe_mac_mar_set(hw, mc_addr_list, i);
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mc_addr_count--;
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- mc_addr_list += PCH_GBE_ETH_ALEN;
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+ mc_addr_list += ETH_ALEN;
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} else {
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/* Clear MAC address mask */
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adrmask = ioread32(&hw->reg->ADDR_MASK);
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