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@@ -523,14 +523,37 @@ static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
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.enable_clpc = 0x00,
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.enable_tx_low_pwr_on_siso_rdl = 0x00,
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.rx_profile = 0x00,
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- .pwr_limit_reference_11_abg = 0xc8,
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- .pwr_limit_reference_11p = 0xc8,
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+ .pwr_limit_reference_11_abg = 0x64,
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+ .per_chan_pwr_limit_arr_11abg = {
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
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+ .pwr_limit_reference_11p = 0x64,
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+ .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
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+ 0xff, 0xff, 0xff },
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.psat = 0,
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- .low_power_val = 0x00,
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- .med_power_val = 0x0a,
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- .high_power_val = 0x11,
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+ .low_power_val = 0x08,
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+ .med_power_val = 0x12,
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+ .high_power_val = 0x18,
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+ .low_power_val_2nd = 0x05,
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+ .med_power_val_2nd = 0x0a,
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+ .high_power_val_2nd = 0x14,
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.external_pa_dc2dc = 0,
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- .number_of_assembled_ant2_4 = 1,
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+ .number_of_assembled_ant2_4 = 2,
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.number_of_assembled_ant5 = 1,
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.tx_rf_margin = 1,
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},
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