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@@ -23,20 +23,21 @@
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#define __WL18XX_CONF_H__
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#define WL18XX_CONF_MAGIC 0x10e100ca
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-#define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0003)
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+#define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0004)
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#define WL18XX_CONF_MASK 0x0000ffff
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#define WL18XX_CONF_SIZE (WLCORE_CONF_SIZE + \
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sizeof(struct wl18xx_priv_conf))
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#define NUM_OF_CHANNELS_11_ABG 150
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#define NUM_OF_CHANNELS_11_P 7
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-#define WL18XX_NUM_OF_SUB_BANDS 9
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#define SRF_TABLE_LEN 16
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#define PIN_MUXING_SIZE 2
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+#define WL18XX_TRACE_LOSS_GAPS_TX 10
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+#define WL18XX_TRACE_LOSS_GAPS_RX 18
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struct wl18xx_mac_and_phy_params {
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u8 phy_standalone;
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- u8 rdl;
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+ u8 spare0;
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u8 enable_clpc;
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u8 enable_tx_low_pwr_on_siso_rdl;
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u8 auto_detect;
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@@ -69,8 +70,8 @@ struct wl18xx_mac_and_phy_params {
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u8 pwr_limit_reference_11_abg;
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u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
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u8 pwr_limit_reference_11p;
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- u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
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- u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS];
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+ u8 spare1[9];
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+ u8 spare2[9];
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u8 primary_clock_setting_time;
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u8 clock_valid_on_wake_up;
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u8 secondary_clock_setting_time;
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@@ -81,7 +82,11 @@ struct wl18xx_mac_and_phy_params {
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s8 low_power_val;
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s8 med_power_val;
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s8 high_power_val;
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- u8 padding[1];
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+ s8 per_sub_band_tx_trace_loss[WL18XX_TRACE_LOSS_GAPS_TX];
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+ s8 per_sub_band_rx_trace_loss[WL18XX_TRACE_LOSS_GAPS_RX];
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+ u8 tx_rf_margin;
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+
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+ u8 padding[4];
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} __packed;
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enum wl18xx_ht_mode {
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